Chip design having integrated fuse and method for the production thereof

#This application is a U.S. National Phase Application under 35 USC 371 of International Application No. PCT/EP2009/065652, filed on 23 Nov. 2009.

#This patent application claims the priority of the German patent application DE 10 2008 064 428.5 filed Dec. 22, 2008, the disclosure content of which is hereby incorporated by reference.

#The invention relates to a chip package and also to a method for the production of a chip package.

#The invention will be explained in detail below using embodiments with reference to the figures. Elements with identical functions or effects here carry identical reference symbols.

#Shown are:

#FIG. 1, a first embodiment of a chip package,

#FIG. 1 shows a general embodiment of a chip package 1. On a semiconductor body 4, an integrated circuit 2 is provided that is coupled with an internal supply connection VDD for the power supply. Furthermore, a reference connection VSS coupled with the integrated circuit 2 is provided that is connected to an external ground connection GND. Between the internal supply connection and the reference connection, a charge storage device 9 is arranged. On the semiconductor body 4, an external supply connection VBAT is further arranged that is connected electrically to the internal supply connection VDD via a fuse 3. The external supply connection VBAT is further connected to an external voltage source SUP that is constructed, for example, as a battery.

#A power supply of the integrated circuit 2 is thus performed by the external voltage source SUP via the external supply connection VBAT and the fuse 3 that is constructed advantageously as a melting fuse. The charge storage device 9 on the internal supply connection VDD is used for the voltage stabilization of the supply voltage on the supply connection VDD. The charge storage device 9 could also be omitted in various embodiments and is not a part of the chip package 1.

#The objective of using fuse 3 is not to protect the integrated circuit 2 from overvoltages. That is accomplished, if necessary, by other components. Instead, fuse 3 is intended to protect the integrated circuit 2 from the consequences of any error states. These could include, for example, short circuits that could lead to dangerous consequences, such as fire. Such error states could occur, in particular, behind the fuse 3, that is, on the connection VDD or within the integrated circuit 2. Overvoltages that are caused by electrostatic discharge, ESD, should not cause the fuse 3 to respond because, after an ESD voltage pulse, a continued functioning of the integrated circuit 2 should be guaranteed.