Stub minimization for assemblies without wirebonds to package substrate

A microelectronic package, comprising:

• a microelectronic element embodying a greater number of active devices to provide memory storage array function than any other function, the microelectronic element having one or more columns of element contacts each column extending in a first direction along a face of the microelectronic element, such that an axial plane normal to the face of the microelectronic element intersects the face of the microelectronic element along a line extending in the first direction and is centered relative to the one or more columns of element contacts;
• a substrate having first and second opposed surfaces and a plurality of substrate contacts at the first surface facing the element contacts and joined thereto;
• a plurality of parallel columns of terminals extending in the first direction at the second surface of the substrate, the terminals electrically connected with the substrate contacts and configured to connect the microelectronic package with a component external to the microelectronic package,
• the terminals including first terminals exposed in a central region of the second surface of the substrate, the first terminals being configured to carry a majority of the address information usable by circuitry within the package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element, and
• wherein the central region has a width in a second direction along the second surface of the substrate transverse to the first direction, the width of the central region not more than three and one-half times a minimum pitch between any two adjacent columns of the parallel columns of the terminals, and the axial plane intersects the central region.