US 8,525,320 B2Granted

Microelectronic die packages with leadframes, including leadframe-based interposer for stacked die packages, and associated systems and methods

AssigneeMicron Technology, Inc.

InventorsMeow Koon Eng, Yong Poo Chia, Suan Jeung Boon, Wuu Yean Tay

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Abstract

Microelectronic die packages, stacked systems of die packages, and methods of manufacturing thereof are disclosed herein. In one embodiment, a method of manufacturing a microelectronic device includes stacking a first die package having a first dielectric casing on top of a second die package having a second dielectric casing, aligning first metal leads at a lateral surface of the first casing with second metal leads at a second lateral surface of the second casing, and forming metal solder connectors that couple individual first leads to individual second leads. In another embodiment, the method of manufacturing the microelectronic device may further include forming the connectors by applying metal solder to a portion of the first lateral surface, to a portion of the second lateral surface, and across a gap between the first die package and the second die package so that the connectors are formed by the metal solder wetting to the individual first leads and the individual second leads.

Claims18

Dependent claims

A stacked system of microelectronic die packages, comprising:

a first die package including a first die and a first dielectric casing at least partially covering the first die, first lateral sides along the first dielectric casing, and first metal contacts having first lateral contact surfaces along the first lateral sides of the first dielectric casing;
a second die package including a second die and a second dielectric casing at least partially covering the second die, second lateral sides along the second dielectric casing, and second metal contacts having second lateral contact surfaces along the second lateral sides of the second dielectric casing, wherein the second die package is stacked on top of the first die package and the first metal contacts are at least generally aligned with corresponding second metal contacts;
a third die package including a third die and a third dielectric casing at least partially covering the third die, third lateral sides along the third dielectric casing, and third metal contacts having third lateral contact surfaces along the third lateral sides of the third dielectric casing wherein the third metal contacts are at least generally aligned with corresponding first metal contacts;
and
metal solder connectors including first-set connectors and second-set connectors, wherein the first-set connectors are coupled to individual first metal contacts and individual second metal contacts, and wherein the second-set connectors are coupled to individual first metal contacts and individual third metal contacts, and wherein at least a portion of the first-set connectors contacts the first and second lateral contact surfaces, and wherein at least a portion of the second-set connectors contacts the first and third lateral contact surfaces, and wherein the first-set connectors are physically and electrically isolated from the individual third metal contacts while the second-set connectors are physically and electrically isolated from the individual second metal contacts.

2 more elements

A stacked system of microelectronic die packages, comprising:

a first die package having a first lateral edge and first metal leads having first contact surfaces flush with the first lateral edge;
a second die package having a second lateral edge and second metal leads having second contact surfaces flush with the second lateral edge, wherein the second contact surfaces are generally aligned with the first lateral contact surfaces;
a third die package having a third lateral edge and third metal leads having third contact surfaces flush with the third lateral edge, wherein the third contact surfaces are generally aligned with the first lateral contact surfaces;
and
external electrically conductive inter-package connectors, including first-set connectors and second-set connectors, wherein the individual first-set connectors are connected to one of the first contact surfaces and a corresponding second contact surface, and wherein the first-set connectors comprise individual metal solder lines that bridge a first gap between the first die package and the second die package, and wherein the individual second-set connectors are connected to one of the first contact surfaces and a corresponding third contact surface, and wherein the second-set connectors comprise individual metal solder lines that bridge a second gap between the first die package and the third die package, and wherein the first-set connectors are physically and electrically isolated from the corresponding third contact surface while the second-set connectors are physically and electrically isolated from the corresponding second contact surface.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/110,060Filed 18 May 2011 · division
Priority: SG 20070600816 Aug 2007
Published: US 2011/0215453 A18 Sep 2011
Granted: 3 Sep 2013
Term ends: Not estimatedThe source records don’t support an estimate.

Classification13 codes

H10W 70/467
Additional interconnections in combination with leadframes: multilayered additional interconnections
H10W 70/09
By depositing layers on the chip or wafer, e.g. "chip-first" RDLs: extending onto an encapsulation that laterally surrounds the chip or wafer,…
H10W 70/424
Shapes or dispositions: cross-sectional shapes
H10W 70/60
Package substrates; Interposers; Redistribution layers [RDL]: insulating or insulated package substrates; Interposers; Redistribution layers

Family

Application11/923,290Parent of this division · filed 24 Oct 2007
US 7,947,529 B2Parent of this division · filed 24 May 2011
US 2011/0215453 A1Pre-grant publication · published 8 Sep 2011
US 2009/0045489 A1Published application
US 8,525,320 B2This patent

From the US filing history. Foreign family members aren’t listed.