MEMS device having chip scale packaging
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChia-Hua Chu, Chung-Hsien Lin
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Abstract
A method and device having chip scale MEMS packaging is described. A first substrate includes a MEMS device and a second substrate includes an integrated circuit. The frontside of the first substrate is bonded to the backside of the second substrate. Thus, the second substrate provides a cavity to encase, protect or operate the MEMS device within. The bond may provide an electrical connection between the first and second substrate. In an embodiment, a through silicon via is used to carry the signals from the first substrate to an I/O connection on the frontside of the second substrate.
Claims19
A device, comprising:
- a first substrate having a MEMS device disposed on a frontside of the first substrate;
- a second substrate including an integrated circuit (IC) and having a frontside and an opposing backside, wherein the IC includes a multi-layer interconnect (MLI) structure, wherein the MLI structure includes:
- a first conductive line,
- a second conductive line overlying the first conductive line,
- a conductive via connecting the first and second conductive line,
- a dielectric material interposing the first and second conductive lines;
- and wherein the second substrate further includes a through-silicon via (TSV) extending from the backside of the second substrate to the first conductive line;
- wherein a first bonding feature on the frontside of the first substrate is bonded to a second bonding feature on a backside of the second substrate;
- and wherein the TSV connects the second bonding feature and the first conductive line.
A method, comprising:
- providing a first substrate having a MEMS device disposed on a frontside of the first substrate;
- providing a second substrate including an integrated circuit and having a backside and an opposing frontside, wherein a multilayer interconnect (MLI) structure is disposed on the frontside of the second substrate, wherein the MLI structure includes a plurality of conductive lines interposed by dielectric material;
- forming a first bonding feature on the frontside of the first substrate;
- forming a second bonding feature on the backside of second substrate;
- forming a through-silicon via (TSV) on the second substrate connecting the second bonding feature and the conductive lines of the MLI structure, wherein the forming the TSV on the second substrate includes exposing a bottom surface of the one of the conductive lines of the MLI structure, wherein another one of the conductive lines of the MLI structure overlies the one of the conductive lines of the MLI structure;
- and wherein the TSV provides for connecting the second bonding feature and an I/O pad formed on the frontside of the second substrate;
- and
- providing an electrical connection between the first substrate and the second substrate by connecting the first bonding feature and the second bonding feature.
A method, comprising:
- providing a first substrate having a MEMS device disposed on a frontside of the first substrate;
- providing a second substrate including features of a circuit formed on a frontside of the second substrate;
- etching a recess in a backside of the second substrate;
- forming a dielectric layer on the backside of the second substrate including in the etched recess;
- and
- bonding the frontside of the first substrate and the backside of the second substrate such that the MEMS device is disposed a cavity defined by the recess, wherein the dielectric layer lines a surface of the cavity.
Dependencies are inferred from the claim text.