US 8,525,251 B2Granted

Nonvolatile programmable logic switch

AssigneeKabushiki Kaisha Toshiba

InventorsDaisuke Hagishima, Atsuhiro Kinoshita, Kazuya Matsuzawa, Kazutaka Ikegami, Yoshifumi Nishi

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Abstract

A nonvolatile programmable logic switch according to an embodiment includes: a memory cell transistor including: a first source region and a first drain region of a second conductivity type formed at a distance from each other in a first semiconductor region of a first conductivity type; a first insulating film, a charge storage film, a second insulating film, and a control gate stacked in this order and formed on the first semiconductor region between the first source region and the first drain region; a pass transistor including: a second source region and a second drain region of a second conductivity type formed at a distance from each other in a second semiconductor region of the first conductivity type; a third insulating film, a gate electrode stacked in this order and formed on the second semiconductor region between the second source region and the second drain region, the gate electrode being electrically connected to the first drain region; and an electrode for applying a substrate bias to the first and second semiconductor regions.

Claims14

Dependent claims

A nonvolatile programmable logic switch comprising:

a device isolation region formed in a semiconductor substrate;
first and second semiconductor regions of a first conductivity type, the first and second semiconductor regions being formed in the semiconductor substrate and being separated from each other by the device isolation region;
a memory cell transistor including:
a first source region and a first drain region of a second conductivity type, the first source region and the first drain region being formed at a distance from each other in the first semiconductor region;
a first insulating film formed on a portion of the first semiconductor region, the portion being located between the first source region and the first drain region;
a charge storage film formed on the first insulating film;
a second insulating film formed on the charge storage film;
and
a control gate formed on the second insulating film;
a pass transistor including:
a second source region and a second drain region of the second conductivity type, the second source region and the second drain region being formed at a distance from each other in the second semiconductor region;
a third insulating film formed on a portion of the second semiconductor region, the portion being located between the second source region and the second drain region;
and
a gate electrode formed on the third insulating film, the gate electrode being electrically connected to the first drain region;
and
an electrode for applying a substrate bias to the first and second semiconductor regions, the electrode being formed in the semiconductor substrate.

13 more elements

A nonvolatile programmable logic switch comprising:

a device isolation region formed in a semiconductor substrate;
first and second semiconductor regions of a first conductivity type, the first and second semiconductor regions being formed in the semiconductor substrate and being separated from each other by the device isolation region;
a memory cell transistor including:
a first source region and a first drain region of a second conductivity type, the first source region and the first drain region being formed at a distance from each other in the first semiconductor region;
a first insulating film formed on a portion of the first semiconductor region, the portion being located between the first source region and the first drain region;
a charge storage film formed on the first insulating film;
a second insulating film formed on the charge storage film;
and
a control gate formed on the second insulating film;
a pass transistor including:
a second source region and a second drain region of the second conductivity type, the second source region and the second drain region being formed at a distance from each other in the second semiconductor region;
a third insulating film formed on a portion of the second semiconductor region, the portion being located between the second source region and the second drain region;
and
a gate electrode formed on the third insulating film;
and
an electrode for applying a substrate bias to the first and second semiconductor regions, the electrode being formed in the semiconductor substrate;
and
a transistor of the first conductivity type and a transistor of the second conductivity type, the transistors being connected in series through a connection node,
wherein the first drain region is electrically connected to gate electrodes of the transistors of the first and second conductivity types, and the gate electrode of the pass transistor is electrically connected to the connection node between the transistors of the first and second conductivity types.

16 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/221,292Filed 30 Aug 2011 · continuation
Priority: JP 2009-07597226 Mar 2009
Published: US 2012/0080739 A15 Apr 2012
Granted: 3 Sep 2013
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10D 30/681
Floating-gate IGFETs: having only two programming levels
G11C 16/0408
Using variable threshold transistors, e.g. FAMOS: comprising cells containing floating gate transistors
H10B 41/30
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the memory core region
H10B 41/40
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the peripheral circuit region