SONOS memory device with reduced short-channel effects

Method of manufacturing a non-volatile memory device on a semiconductor substrate, the non-volatile memory device comprising a source region, a drain region, a channel region, a memory element, and a gate, the channel region extending in a first direction between the source region and the drain region and being disposed within a beam-shaped semiconductor layer having a portion thereof free-standing over a gap region between the portion and the substrate;

• the gate being disposed near the channel region;
• the memory element being disposed in between the channel region and the gate,
• the method comprising the steps of:
• creating the beam-shaped semiconductor layer for accommodating the channel region, the beam-shaped semiconductor layer extending in the first directions between source and drain regions and having lateral surfaces that extend parallel to the first direction and having the portion thereof free-standing over the substrate, and
• providing as a memory element a charge-trapping stack between the channel region and the gate, which covers said lateral surfaces, with at least a lower surface directed towards the semiconductor surface layers and side surfaces being directly connecting to the lower surface so as to embed the beam-shaped semiconductor layer in a U-shaped form of the charge trapping stack.

An apparatus comprising:

• an elongated structure having a portion thereof free-standing over an underlying material and separated therefrom by a gap region, the elongated structure including doped regions free-standing over the underlying material, the doped regions including source and drain regions separated by a channel region;
• a charge-trapping stack around the channel region of the elongated structure and having a lower portion thereof between the elongated structure and the underlying material, the charge-trapping stack being configured and arranged to store charge as a non-volatile memory value;
• and
• a gate around the charge-trapping stack and including a portion between the charge-trapping stack and the underlying material, the gate and the charge-trapping stack being between the free-standing portions of the elongated structure that include the doped source and drain regions.