Method of forming a planar field effect transistor with embedded and faceted source/drain stressors on a silicon-on-insulator (SOI) wafer, a planar field effect transistor structure and a design structure for the planar field effect transistor

A design structure tangibly embodied in a machine readable medium for designing, manufacturing, and/or testing an integrated circuit, said design structure comprising at least instructions that, when executed by a computer-aided design system, generate a machine-executable representation of a field effect transistor, said field effect transistor comprising

• a substrate;
• an insulator layer on said substrate;
• a semiconductor layer on said insulator layer, said semiconductor layer comprising:
• a channel region;
• recesses on opposing sides of said channel region, said recesses having inner sidewalls positioned laterally adjacent to said channel region with each inner sidewall having a faceted profile, said recesses further having bottom surfaces separated from said insulator layer by a distance and said semiconductor layer have doped regions between said bottom surfaces and said insulator layer;
• and
• a semiconductor material within said recesses, said semiconductor material being pre-selected so as to impart one of tensile stress and compressive stress on said channel region.

A field effect transistor comprising:

• a substrate;
• an insulator layer on said substrate;
• a semiconductor layer on said insulator layer, said semiconductor layer comprising:
• a channel region;
• and
• recesses on opposing sides of said channel region, said recesses having inner sidewalls positioned laterally adjacent to said channel region with each inner sidewall having a faceted profile;
• a semiconductor material within said recesses, said semiconductor material being pre-selected so as to impart one of tensile stress and compressive stress on said channel region,
• said recesses further having bottom surfaces separated from said insulator layer by a distance;
• and
• said semiconductor layer further comprising doped regions immediately adjacent to and aligned with said bottom surfaces only of said recesses such that said doped regions are positioned between said bottom surfaces of said recesses and said insulator layer and are further not positioned between said inner sidewalls of said recesses and said channel region, wherein a thickness of said doped regions is less than said distance such that said doped regions do not contact said insulator layer.