Thin-film transistor array substrate, organic light-emitting display device comprising the thin-film transistor array substrate, and method of manufacturing the thin-film transistor array substrate

An organic light-emitting display device, comprising:

• an active layer of a thin-film transistor (TFT) disposed on a substrate and a lower electrode of a capacitor disposed at a same level as the active layer on the substrate;
• a first insulation layer disposed on the active layer and the lower electrode and having a first gap exposing an area of the lower electrode;
• a gate electrode of the TFT disposed on the first insulation layer, and an upper electrode of the capacitor disposed on the lower electrode and the first insulation layer, the upper electrode of the capacitor having a second gap that exposes a portion of the first insulation layer and the first gap;
• a source electrode and a drain electrode electrically connected to source and drain regions of the active layer;
• a second insulation layer disposed between the gate electrode and the source electrode and between the gate electrode and the drain electrode, wherein the second insulation layer is not disposed on the upper electrode of the capacitor, in the first gap of the first insulation layer or in the second gap of the upper electrode;
• a pixel electrode connected to the source electrode or the drain electrode;
• a third insulation layer that covers the source electrode and the drain electrode and exposes the pixel electrode;
• an organic emission layer disposed on the pixel electrode;
• and
• a counter electrode disposed on the organic emission layer.

A method of manufacturing a TFT array substrate, the method comprising:

• a first mask process of forming a semiconductor layer on a substrate and patterning the semiconductor layer to form an active layer of a TFT and a lower electrode of a capacitor;
• a second mask process of forming a first insulation layer, stacking a first metal on the first insulation layer, and patterning the first metal to form a gate electrode of the TFT and an etch stop layer of the capacitor with a first gap in an area of the lower electrode;
• a third mask process of forming a second insulation layer to have contact holes by which a source region and a drain region of the active layer are exposed and by which the etch stop layer and the first gap are exposed;
• a fourth mask process of forming a second metal on a result of the third mask process, patterning the second metal to form a source electrode and a drain electrode respectively connected to the source region and the drain region, and removing the first metal and the etch stop layer without removing the source and drain electrodes;
• and
• a fifth mask process of forming a third metal on a result of the fourth mask process and patterning the third metal to form a pixel electrode and to form an upper electrode on the first insulation layer, the upper electrode including a second gap that exposes the first insulating layer and the first gap;
• and
• a sixth mask process of forming a third insulation layer and patterning the third insulation layer to expose the pixel electrode.