Thin film transistor array panel

A thin film transistor array panel comprising:

• a plurality of pixel electrodes arranged in a matrix;
• a plurality of data lines extending in a first direction such that one data line is disposed per two pixel electrode columns;
• and
• a plurality of gate lines extending in a second direction and disposed in pairs per one pixel electrode row,
• where first and second pixel electrodes, among the plurality of data lines, neighbor each other in the second direction with the first data line interposed therebetween,
• a first gate line and a second gate line disposed at a first pixel electrode row where the first pixel electrode and the second pixel electrode are disposed,
• the first pixel electrode is connected to a first thin film transistor including a first source electrode connected to the first data line, a first drain electrode facing the first source electrode, and a first gate electrode,
• the second pixel electrode is connected to a second thin film transistor including a second source electrode connected to the first data line, the second drain electrode facing the second source electrode, and a second gate electrode,
• a relative position of the first source electrode with respect to the first drain electrode is the same as a relative position of the second source electrode with respect to the second drain electrode,
• the first source electrode is connected to the data line through a first source connection, and the second source electrode is connected to the data line through a second source connection, and
• the first source connection is longer than the second source connection.