US 8,525,092 B2Granted

Data processing method and solid-state image pickup device

AssigneeOlympus Corporation

InventorYoshio Hagihara

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Abstract

A data processing method may include counting one of a plurality of clock signals with a first mode, counting clock signals based on a predetermined number of the plurality of clock signals with the first mode, to output a first clock signal every time a counter value becomes a first predetermined value, counting the first clock signal with the first mode, counting one of the clock signals with a second mode while the counted value is considered as a first initial value, counting clock signals based on the predetermined number of the plurality of clock signals with the second mode, to output a second clock signal every time the counter value becomes a second predetermined value while the counted value is considered as a second initial value, counting the second clock signal with the second mode, and outputting the counter values with the second mode as difference data between a first data signal and a second data signal.

Claims4

Dependent claims

A data processing method that performs a differential processing between a first data signal and a second data signal based on an output of a delay circuit, the delay circuit including a plurality of inverting elements that are connected to each other, the data processing method comprising:

a first data processing on the first data signal, the first data processing comprising:
counting, by an upper counting unit, one of a plurality of clock signals output from the delay circuit with a first mode, the first mode being either one of a down-count mode and an up-count mode;
counting, by a lower counting unit, clock signals based on a predetermined number of the plurality of clock signals output from the delay circuit with the first mode, to output a first clock signal to the upper counting unit every time a counter value becomes a first predetermined value;
and
counting, by the upper counting unit, the first clock signal from the lower counting unit with the first mode;
a second data processing on the second data signal, the second data processing comprising:
counting, by the upper counting unit, one of the plurality of clock signals output from the delay circuit with a second mode, the second mode being the other one of the either one of the down-count mode and the up-count mode, while the value counted with the first mode is considered as a first initial value;
counting, by the lower counting unit, clock signals based on the predetermined number of the plurality of clock signals output from the delay circuit with the second mode, to output a second clock signal to the upper counting unit every time the counter value becomes a second predetermined value while the value counted with the first mode is considered as a second initial value;
and
counting, by the upper counting unit, the second clock signal from the lower counting unit with the second mode;
and
outputting the counter values counted by the upper counting unit and the lower counting unit with the second mode as difference data between the first data signal and the second data signal.

9 more elements

A solid-state image pickup device, comprising:

a image capturing unit comprising a plurality of pixels which output pixel signals based on the amount of incident electromagnetic waves, arranged in a matrix shape;
a reference signal generation unit configured to generate a reference signal that increases or decreases through time;
a comparison unit configured to perform a comparison between the pixel signals output from the pixels and the reference signal, which are to be A/D converted, and ends the comparison at a timing that the reference signal satisfies a predetermined condition with respect to the pixel signal;
a delay circuit having a plurality of inverting elements;
an upper counting unit configured to perform counting of clock signals from the delay circuit;
a lower latching unit configured to latch a predetermined number of clock signals output from the delay circuit at a timing based on the end of the comparison processing;
and
a lower counting unit configured to perform counting of clock signals based on the predetermined number of the clock signals latched by the lower latching unit,
wherein a data processing method, which is performed by the upper counting unit and the lower counting unit, comprises:
a first data processing on a first data signal, the first data processing comprising:
counting, by the upper counting unit, one of a plurality of clock signals output from the delay circuit with a first mode, the first mode being either one of a down-count mode and an up-count mode;
counting, by the lower counting unit, clock signals based on a predetermined number of the plurality of clock signals that is latched by the lower latching unit with the first mode, to output a first clock signal to the upper counting unit every time a counter value becomes a first predetermined value;
and
counting, by the upper counting unit, the first clock signal from the lower counting unit with the first mode;
a second data processing on a second data signal, the second data processing comprising:
counting, by the upper counting unit, one of the plurality of clock signals output from the delay circuit with a second mode, the second mode being the other one of the either one of the down-count mode and the up-count mode, while the value counted with the first mode is considered as a first initial value;
counting, by the lower counting unit, clock signals based on the predetermined number of the plurality of clock signals that is latched by the lower latching unit with the second mode, to output a second clock signal to the upper counting unit every time the counter value becomes a second predetermined value while the value counted with the first mode is considered as a second initial value;
and
counting, by the upper counting unit, the second clock signal from the lower counting unit with the second mode;
and
outputting the counter values counted by the upper counting unit and the lower counting unit with the second mode as difference data between the first data signal and the second data signal that are based on the output from the delay circuit according to the pixel signals.

18 more elements

Dependencies are inferred from the claim text.