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US 8,524,595 B2Granted
Semiconductor package structures
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsMirng-Ji Lii, Hsin-Hui Lee
Life of this patent
Estimating the term…
Abstract
A semiconductor structure includes a plurality of solder structures between a first substrate and a second substrate. A first encapsulation material is substantially around a first one of the solder structures and a second encapsulation material is substantially around a second one of the solder structures. The first one and the second one of the solder structures are near to each other and a gap is between the first encapsulation material and the second encapsulation material.
Claims20
A semiconductor method, comprising:
- forming a plurality of solder balls or solder bumps over a first substrate;
- forming a planar layer of encapsulation material over the first substrate, partially covering the solder balls or solder bumps, the planar layer extending an entire distance between a first one of the solder balls or solder bumps and a second one of the solder balls or solder bumps;
- flowing the planar layer of encapsulation material along at least one side wall of at least the first and second ones of the solder balls or solder bumps, to form a first encapsulation material portion around the first solder ball or solder bump and a second encapsulation material portion around the second solder ball or solder bump, wherein the first and second solder balls or solder bumps are near to each other and a gap is formed between the first and second encapsulation material portions.
A semiconductor method, comprising:
- forming a plurality of solder structures over a first substrate;
- forming a planar layer of encapsulation material over the first substrate, partially covering the solder structures;
- flipping the first substrate after forming the planar layer of encapsulation material;
- thermally treating the planar layer of encapsulation material over a second substrate so as to melt the encapsulation material to flow along at least one side wall of at least first and second ones of the solder structures, to form a first encapsulation material portion around the first solder structure and a second encapsulation material portion around the second solder structure, wherein the first and second solder structures are near to each other and a gap is formed between the first and second encapsulation material portions;
- and
- reflowing the solder structures over the second substrate for electrical connection.
3 more elements
A semiconductor method, comprising:
- forming a plurality of solder structures over a first substrate;
- forming a planar layer of encapsulation material over the first substrate, partially covering the solder structures, the planar layer extending an entire distance between a first one of the solder structures and a second one of the solder structures at a time the encapsulation material forming the planar layer is deposited;
- flowing the planar layer of encapsulation material along at least one side wall of at least the first and second ones of the solder structures after the encapsulation material forming the planar layer is deposited, to form a first encapsulation material portion around the first solder structure and a second encapsulation material portion around the second solder structure, so the planar layer no longer extends the entire distance after the flowing, wherein the first and second solder structures are near to each other and, and a gap is formed between the first and second encapsulation material portions.
Dependencies are inferred from the claim text.