Non-uniformity reduction in semiconductor planarization
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsNeng-Kuo Chen, Jeff J. Xu
Life of this patent
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Abstract
Provided is a method of planarizing a semiconductor device. The method includes providing a substrate. The method includes forming a first layer over the substrate. The method includes forming a second layer over the first layer. The first and second layers have different material compositions. The method includes forming a third layer over the second layer. The method includes performing a polishing process on the third layer until the third layer is substantially removed. The method includes performing an etch back process to remove the second layer and a portion of the first layer. Wherein an etching selectivity of the etch back process with respect to the first and second layers is approximately 1:1.
Claims20
A method, comprising:
- forming a first layer over a first region and a second region of a substrate, the first and second regions having different pattern densities;
- forming a second layer over the first layer, the first and second layers containing different materials;
- forming a third layer over the second layer, the third and second layers containing different materials;
- polishing the third layer, the second layer serving as a polishing-stop layer during the polishing, wherein remaining portions of the third layer and the second layer collectively form a substantially planar surface at an end of the polishing;
- and
- thereafter removing the remaining portions of the third layer and the second layer and a portion of the first layer, wherein a remaining portion of the first layer after the removing maintains a substantially planar surface.
A method of fabricating a semiconductor device, comprising:
- forming a first layer over a wafer that has a plurality of regions having non-uniform pattern densities;
- forming a second layer over the first layer, the first and second layers having different material compositions;
- forming a third layer over the second layer, the second and third layers having different material compositions, the third and first layers having substantially similar material compositions;
- planarizing the third layer while the second layer serves as a polishing-stop layer, wherein the second layer and remaining portions of the third layer collectively have a total surface variation of less than about 100 Angstroms;
- and
- etching back the second layer and a portion of the first layer until a predetermined thickness for a remaining portion of first layer has been reached, wherein the remaining portion of the first layer has a surface profile substantially similar to a collective surface of the second layer and the remaining portions of the third layer after the planarizing.
A method of planarizing a semiconductor device to make it suitable for a 15-nm technology node or smaller, comprising:
- forming a first layer over a first region and a second region of a substrate, the first and second regions having different pattern densities, wherein the first layer has a first thickness in a range from about 500 Angstroms to about 4000 Angstroms;
- forming a second layer over the first layer, the first and second layers containing different materials, wherein the second layer has a second thickness in a range from about 20 Angstroms to about 200 Angstroms;
- forming a third layer over the second layer, the third and second layers containing different materials, the third and first layers containing substantially identical materials, wherein the third layer has a third thickness in a range from about 300 Angstroms to about 3000 Angstroms;
- performing a polishing process to the third layer, the second layer serving as a polishing-stop layer during the polishing process, wherein remaining portions of the third layer and the second layer collectively form a surface having a surface variation of less than about 100 Angstroms at a completion of the polishing process;
- and
- thereafter performing an etch back process to the first, second, and third layers until a remaining portion of the first layer reaches a predetermined thickness level, wherein the remaining portion of the first layer has a surface variation of less than about 100 Angstroms at a completion of the etch back process, and wherein the etch back process includes the following process parameters:
- an etchant that includes a gas mixture of tetrafluoromethane (CF4) and trifluoromethane (CHF3), wherein a ratio of the CF4 gas and the CHF3 gas is in a range from about 0 to about 1;
- a radio-frequency (RF) power that is in a range from about 200 watts to about 600 watts;
- and
- a bias voltage from about 50 volts to about 250 volts.
Dependencies are inferred from the claim text.