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US 8,524,569 B2Granted
Methods of forming an isolation layer and methods of manufacturing semiconductor devices having an isolation layer
AssigneeSamsung Electronics Co., Ltd.
InventorsDae-Hyuk Kang, Jung-Won Lee, Bo-Un Yoon, Kun-Tack Lee
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Abstract
In a method of forming an isolation layer, first and second trenches are formed on a substrate. The first and the second trenches have first and second widths, respectively, and the second width is greater than the first width. A second isolation layer pattern partially fills the second trench. A first isolation layer pattern and the third isolation layer pattern are formed. The first isolation layer pattern fills the first trench, and the third isolation layer pattern is formed on the second isolation layer pattern and fills a remaining portion of the second trench.
Claims14
A method of forming an isolation layer, comprising:
- forming a first trench and a second trench at upper portions of a substrate, the first and the second trenches having first and second widths, respectively, and the second width being greater than the first width;
- forming a first isolation layer pattern filling the first trench;
- forming a second isolation layer pattern partially filling the second trench;
- and
- forming a third isolation layer pattern on the second isolation layer pattern and filling a remaining portion of the second trench;
- wherein forming the first and the second trenches on the substrate comprises:
- forming a plurality of first structures and a plurality of second structures on the substrate;
- wherein forming the second isolation layer pattern comprises:
- forming a first insulation layer on the substrate, the first structures and the second structures, the first insulation layer filling the first and the second trenches, a first space between the first structures, and a second space between the second structures;
- planarizing an upper portion of the first insulation layer using the first and the second structures as a planarization endpoint to form a first insulation layer pattern and a second insulation layer pattern, the first insulation layer pattern being formed between the first structures and in the first trench, and the second insulation layer pattern being formed between the second structures and in the second trench;
- and
- removing the first insulation layer pattern and an upper portion of the second insulation layer pattern;
- wherein forming the first insulation layer comprises:
- forming the first insulation layer having a void therein to partially fill the first trench and the first space between the first structures.
11 more elements
A method of manufacturing a semiconductor device, comprising:
- forming a plurality of first structures and a plurality of second structures on a substrate in a first region and a second region, respectively, the first structures being spaced apart from each other at a first distance, the second structures being spaced apart from each other at a second distance greater than the first distance, each of the first structures having a first tunnel insulation layer pattern and a first floating gate sequentially stacked on the substrate, and each of the second structures having a second tunnel insulation layer pattern and a second floating gate sequentially stacked on the substrate;
- removing upper portions of the substrate using the first and the second structures as etching masks to form a first trench and a second trench in the first and second regions, respectively, the first trench having a first width and the second trench having a second width greater than the first width;
- forming a first isolation layer pattern filling the first trench;
- forming a second isolation layer pattern partially filling the second trench;
- forming a third isolation layer pattern on the second isolation layer pattern and filling a remaining portion of the second trench;
- forming a first dielectric layer pattern and a second dielectric layer pattern, the first dielectric layer pattern being formed on the first floating gate and the first isolation layer pattern, and the second dielectric layer pattern being formed on the second floating gate;
- and
- forming a first control gate and a second control gate on the first and the second dielectric layer patterns, respectively.
5 more elements
Dependencies are inferred from the claim text.