Methods for the fabrication of integrated circuits including back-etching of raised conductive structures

A method for fabricating an integrated circuit, comprising:

• producing a partially-completed semiconductor device including a substrate, source/drain (S/D) regions, a channel region between the S/D regions, a gate stack over the channel region, and sidewall spacers adjacent opposing sides of the gate stack;
• etching cavities into the S/D regions;
• epitaxially growing bodies of strain material over the substrate, each body of strain material having an embedded region substantially filling the cavity and a freestanding overgrowth region adjacent the sidewall spacers;
• removing the sidewall spacers to create lateral gaps between the gate stack and the freestanding overgrowth regions;
• and
• back-etching each freestanding overgrowth regions to increase the widths of the lateral gaps such that any parasitic fringing capacitances created between the freestanding strain material overgrowth regions and the gate stack during operation of the completed semiconductor device are reduced.

A method for fabricating an integrated circuit, comprising:

• producing a partially-completed semiconductor device including an ultra-thin silicon-on-insulator (SOI) substrate, source/drain (S/D) regions, a channel region between the S/D regions, a gate stack over the channel region, and sidewall spacers adjacent opposing sides of the gate stack;
• epitaxially growing raised source/drain regions over the S/D regions of the ultra-thin SOI substrate adjacent the sidewall spacers;
• removing the sidewall spacers to create a lateral gap between the gate stack and each raised S/D region;
• and
• back-etching each raised S/D regions to increase the width of the lateral gaps such that any parasitic fringing capacitances created between the raised S/D regions and the gate stack during operation of the completed semiconductor device are reduced.