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US 8,524,562 B2Granted
Method for reducing Fermi-Level-Pinning in a non-silicon channel MOS device
AssigneeImec
InventorsWei-E Wang, Han Chung Lin, Marc Meuris
Life of this patent
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Abstract
A method to reduce (avoid) Fermi Level Pinning (FLP) in high mobility semiconductor compound channel such as Ge and III-V compounds (e.g. GaAs or InGaAs) in a Metal Oxide Semiconductor (MOS) device. The method is using atomic hydrogen which passivates the interface of the high mobility semiconductor compound with the gate dielectric and further repairs defects. The methods further improve the MOS device characteristics such that a MOS device with a quantum well is created.
Claims20
A method for reducing Fermi Level Pinning in a high mobility metal oxide semiconductor device, the method comprising:
- providing a high mobility semiconductor on a substrate to form a channel of the metal oxide semiconductor device, wherein the high mobility semiconductor is selected from the group consisting of Ge, SiGe, Group III-V compounds, and combinations thereof;
- forming a gate dielectric on the high mobility semiconductor;
- providing a gate electrode onto the gate dielectric to form a gate of the metal oxide semiconductor device, wherein the gate electrode comprises a noble metal;
- and thereafter
- performing an anneal with atomic hydrogen for at least 5 minutes, wherein the anneal is performed using a catalytic forming gas anneal in a presence of the noble metal.
2 more elements
Dependencies are inferred from the claim text.