Split gate with different gate materials and work functions to reduce gate resistance of ultra high density MOSFET
AssigneeAlpha and Omega Semiconductor Incorporated
InventorsSung-Shan Tai, YongZhong Hu
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Abstract
This invention discloses a trenched metal oxide semiconductor field effect transistor (MOSFET) cell. The trenched MOSFET cell includes a trenched gate opened from a top surface of the semiconductor substrate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The trenched gate further includes at least two mutually insulated trench-filling segments each filled with materials of different work functions. In an exemplary embodiment, the trenched gate includes a polysilicon segment at a bottom portion of the trenched gate and a metal segment at a top portion of the trenched gate.
Claims9
A method for manufacturing a semiconductor power device comprising:
- opening and filling a high-temperature sustainable dielectric layer into trenches followed by carrying out processes of implanting and diffusing a body and source regions and removing a top portion of said high-temperature sustainable dielectric layer in said trenches to form a bottom polysilicon segment prior to carrying out processes of forming a metal gate on a top portion of said trenches thus minimizing high-temperature cycles applied to said metal gate;
- and
- lining a polysilicon layer over trench side walls before forming said metal gate on top portion of said trenches.
A method for manufacturing a semiconductor power device comprising:
- opening and filling a high-temperature sustainable dielectric layer into trenches followed by carrying out processes of implanting and diffusing a body and source regions and removing a top portion of said high-temperature sustainable dielectric layer in said trenches to form a bottom polysilicon segment prior to carrying out processes of forming a metal gate on a top portion of said trenches thus minimizing high-temperature cycles applied to said metal gate;
- and
- forming an inter-gate insulation layer by applying a high temperature oxide (HTO) deposition on top of said bottom dielectric gate before carrying out processes to form said metal gate on top of said inter-gate insulation layer.
A method for manufacturing a semiconductor power device comprising:
- opening and filling a high-temperature sustainable dielectric layer into trenches followed by carrying out processes of implanting and diffusing a body and source regions and removing a top portion of said high-temperature sustainable dielectric layer in said trenches to form a bottom polysilicon segment prior to carrying out processes of forming a metal gate on a top portion of said trenches thus minimizing high-temperature cycles applied to said metal gate;
- and
- said step of carrying out processes of forming a metal gate on a top portion of said trenches further comprising applying a chemical vapor deposition (CVD) process for depositing a Ti/TiN/W into said trenches to form said metal gate above said bottom dielectric gate.
Dependencies are inferred from the claim text.