Integration technique using thermal oxide select gate dielectric for select gate and replacement gate for logic

A method of making a logic transistor in a logic region of a substrate and a non-volatile memory (NVM) cell in an NVM region of the substrate, comprising:

• forming a control gate overlying a charge storage layer over the substrate in the NVM region, wherein the control gate comprises polysilicon;
• forming an oxide spacer on a sidewall of the control gate;
• thermally growing an oxygen-containing layer on the substrate and on the control gate;
• forming a polysilicon layer over the oxygen-containing layer in the NVM region and the logic region;
• planarizing the polysilicon layer;
• forming a patterned masking layer in the NVM region and the logic region, wherein the patterned masking layer comprises a first masking portion formed over the polysilicon layer and control gate in the NVM region and a second masking portion over the polysilicon layer in the logic region, wherein:
• the first masking portion is directly over the control gate and a first edge of the first masking portion extends laterally from the control gate onto the polysilicon layer to define a select gate location laterally adjacent the control gate in the NVM region;
• and
• the second masking portion defines a logic gate location in the logic region;
• using the patterned masking layer to remove exposed portions of the polysilicon layer, wherein a first portion of the polysilicon layer remains at the select gate location to form a select gate and a second portion of the polysilicon layer remains at the logic gate location;
• forming a dielectric layer in the NVM region and the logic region, wherein the dielectric layer is formed over the select gate, the control gate, and the second portion of the polysilicon layer;
• planarizing the dielectric layer to expose the second portion of the polysilicon layer;
• forming a protection layer over the select gate and the control gate in the NVM region, wherein the protection layer exposes the logic region;
• removing the second portion of the polysilicon layer and a portion of the oxygen-containing layer to result in an opening at the logic gate location;
• forming a high-k gate dielectric layer over the protection layer in the NVM region and over the dielectric layer and within the opening in the logic region;
• and
• forming a logic gate in the logic region within the opening and over the high-k gate dielectric layer.

A method of making a logic transistor in a logic region of a substrate and a non-volatile memory (NVM) cell in an NVM region of the substrate, comprising:

• forming a nanocrystal stack layer over the substrate in the NVM region and the logic region;
• forming a first polysilicon layer over the nanocrystal stack layer in the NVM region and the logic region;
• patterning the first polysilicon layer and the nanocrystal stack layer to form a control gate in the NVM region and to remove the first polysilicon layer and the charge storage layer from the logic region;
• forming a thermally-grown oxygen-containing dielectric layer over the substrate and the control gate in the NVM region and over the substrate in the logic region;
• forming a second polysilicon layer over the oxygen-containing dielectric layer in the NVM region and the logic region;
• planarizing the second polysilicon layer, wherein the oxygen-containing dielectric layer comprises a sidewall portion located along the sidewall of the control gate;
• forming a patterned masking layer in the NVM region and the logic region, wherein the patterned masking layer comprises a first masking portion formed over the second polysilicon layer and the control gate in the NVM region and a second masking portion over the second polysilicon layer in the logic region, wherein:
• the first masking portion is directly over the control gate and a first edge of the first masking portion extends laterally from the control gate onto the second polysilicon layer to define a select gate location laterally adjacent the control gate in the NVM region;
• and
• the second masking portion defines a logic gate location in the logic region;
• using the patterned masking layer to remove exposed portions of the second polysilicon layer, wherein a first portion of the second polysilicon layer remains at the select gate location to form a select gate and a second portion of the second polysilicon layer remains at the logic gate location;
• forming a dielectric layer in the NVM region and the logic region, wherein the dielectric layer is formed over the select gate, the control gate, and the second portion of the second polysilicon layer;
• planarizing the dielectric layer to expose the second portion of the second polysilicon layer;
• forming a protection layer over the select gate and the control gate in the NVM region and over the second polysilicon layer in the logic region;
• patterning the protection layer to remove portions of the protection layer from the logic region;
• removing the second portion of the second polysilicon layer and a portion of the thermally-grown oxygen-containing dielectric layer to result in an opening at the logic gate location;
• forming a high-k gate dielectric layer over the protection layer in the NVM region and over the dielectric layer and within the opening in the logic region;
• and
• forming a logic gate in the logic region within the opening and over the high-k gate dielectric layer.