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AssigneesImec, Samsung Electronics Co., Ltd., Taiwan Semiconductor Manufacturing Company, Ltd.
InventorsHag-Ju Cho, Anabela Veloso, HongYu Yu, Stefan Kubicek, Shou-Zen Chang
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A dual work function semiconductor device and method for fabricating the same are disclosed. In one aspect, a device includes a first and second transistor on a first and second substrate region. The first and second transistors include a first gate stack having a first work function and a second gate stack having a second work function respectively. The first and second gate stack each include a host dielectric, a gate electrode comprising a metal layer, and a second dielectric capping layer therebetween. The second gate stack further has a first dielectric capping layer between the host dielectric and metal layer. The metal layer is selected to determine the first work function. The first dielectric capping layer is selected to determine the second work function.
A method of manufacturing a dual work function semiconductor device having a substrate with a first region and a second region, the method comprising:
A method of manufacturing a dual work function semiconductor device, the method comprising:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
Having a compositional variation, e.g. multilayered: being perpendicular to the channel plane
The components including insulated gates, e.g. IGFETs: manufacturing their gate insulating layers
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their gate insulating layers
About 2 years 3 months of term left · ends 22 Jan 2029 (estimated)
1. Field of the Invention
The invention is related to methods of manufacturing semiconductor devices. Particularly, the invention is related to dual work function semiconductor devices having a gate stack comprising high-k materials and a single metal gate electrode.
2. Description of the Related Technology
All drawings are intended to illustrate some inventive aspects and embodiments. The drawings described are only schematic and are non-limiting.
FIGS. 1(a), (b), (c) represent schematically the gate stack of a semiconductor device comprising two regions (I, II), a host dielectric layer (1), a first capping layer (2), a second capping layer (3) and a metal gate electrode (4).
FIGS. 2(a), (b), (c) represent schematically the gate stack of a semiconductor device comprising two regions (I, II), a host dielectric layer (1), a first capping layer (2), a buffer layer (5), a second capping layer (3) and a metal gate electrode (4).
The present invention will be described with respect to particular embodiments and with reference to certain drawings but the invention is not limited thereto but only by the claims. Any reference signs in the claims shall not be construed as limiting the scope. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes.
Where the term “comprising” is used in the present description and claims, it does not exclude other elements or steps. Where an indefinite or definite article is used when referring to a singular noun e.g. “a” or “an”, “the”, this includes a plural of that noun unless something else is specifically stated.
Furthermore, the terms first, second and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a sequence, either temporally, spatially, in ranking or in any other manner. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the invention described herein are capable of operation in other sequences than described or illustrated herein.