Back to results
US 8,524,544 B2Granted
MOSFET with a nanowire channel and fully silicided (FUSI) wrapped around gate
AssigneeInternational Business Machines Corporation
InventorsSarunya Bangsaruntip, Guy Cohen
Life of this patent
Estimating the term…
Abstract
Nanowire-channel metal oxide semiconductor field effect transistors (MOSFETs) and techniques for the fabrication thereof are provided. In one aspect, a MOSFET includes a nanowire channel; a fully silicided gate surrounding the nanowire channel; and a raised source and drain connected by the nanowire channel. A method of fabricating a MOSFET is also provided.
Claims16
A method of fabricating a MOSFET, comprising the steps of:
- forming a nanowire channel by patterning a fin in a wafer comprising a first poly-silicon layer, a first dielectric layer over the first poly-silicon layer, a silicon-on-insulator layer over the first dielectric layer, a second dielectric layer over the silicon-on-insulator layer and a second poly-silicon layer over the second dielectric layer, wherein the patterned silicon-on-insulator layer forms a nanowire, a portion of which serves as the channel;
- forming a fully silicided gate surrounding the nanowire channel by:
- (a) forming poly-silicon spacers on opposite sides of the fin, (b) depositing a metal stack over a portion of the fin by:
- depositing a silicide forming metal layer over the fin, depositing a capping layer having a thickness of from about 2 nm to about 25 nm over the silicide forming metal layer, and depositing an oxide cap layer over the capping layer, such that the metal stack comprises a silicide forming metal in contact with the patterned first and second poly-silicon layers and with the poly-silicon spacers, and (c) converting the first and second poly-silicon layers and the poly-silicon spacers to a silicide by annealing the metal stack to react the silicide forming metal with the patterned first and second poly-silicon layers and the poly-silicon spacers to form metal silicide regions adjacent to a top, bottom and sides of the portion of the nanowire that serves as the channel;
- and
- forming a raised source and drain connected by the nanowire channel.
3 more elements
A method of fabricating a MOSFET, comprising the steps of:
- forming a nanowire channel by patterning a fin in a wafer comprising a first poly-silicon layer, a first dielectric layer over the first poly-silicon layer, a silicon-on-insulator layer over the first dielectric layer, a second dielectric layer over the silicon-on-insulator layer and a second poly-silicon layer over the second dielectric layer, wherein the patterned silicon-on-insulator layer forms a nanowire, a portion of which serves as the channel;
- forming a fully silicided gate surrounding the nanowire channel by:
- (a) forming poly-silicon spacers on opposite sides of the fin, (b) depositing a metal stack over a portion of the fin by:
- depositing a silicide forming metal layer over the fin, depositing a capping layer over the silicide forming metal layer, and depositing an oxide cap layer to a thickness of from about 20 nm to about 100 nm over the capping layer, such that the metal stack comprises a silicide forming metal in contact with the patterned first and second poly-silicon layers and with the poly-silicon spacers, and (c) converting the first and second poly-silicon layers and the poly-silicon spacers to a silicide by annealing the metal stack to react the silicide forming metal with the patterned first and second poly-silicon layers and the poly-silicon spacers to form metal silicide regions adjacent to a top, bottom and sides of the portion of the nanowire that serves as the channel;
- and
- forming a raised source and drain connected by the nanowire channel.
3 more elements
Dependencies are inferred from the claim text.