Display device and electronic device
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorsAtsushi Umezaki, Hiroyuki Miyake
Life of this patent
Estimating the term…
Abstract
An object of the invention is to provide a circuit technique which enables reduction in power consumption and high definition of a display device. A switch controlled by a start signal is provided to a gate electrode of a transistor, which is connected to a gate electrode of a bootstrap transistor. When the start signal is input, a potential is supplied to the gate electrode of the transistor through the switch, and the transistor is turned off. The transistor is turned off, so that leakage of a charge from the gate electrode of the bootstrap transistor can be prevented. Accordingly, time for storing a charge in the gate electrode of the bootstrap transistor can be shortened, and high-speed operation can be performed.
Claims16
A display device comprising:
- a pixel;
- and
- a driver circuit,
- wherein the driver circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor;
- a first terminal of the first transistor is electrically connected to a fourth wiring, and a second terminal of the first transistor is electrically connected to a third wiring;
- a first terminal of the second transistor is electrically connected to a sixth wiring, and a second terminal of the second transistor is electrically connected to the third wiring;
- a first terminal of the third transistor is electrically connected to a seventh wiring, a second terminal of the third transistor is electrically connected to a gate of the second transistor, and a gate of the third transistor is electrically connected to the seventh wiring;
- a first terminal of the fourth transistor is electrically connected to the sixth wiring, a second terminal of the fourth transistor is electrically connected to the gate of the second transistor, and a gate of the fourth transistor is electrically connected to a gate of the first transistor;
- a first terminal of the fifth transistor is electrically connected to a fifth wiring, a second terminal of the fifth transistor is electrically connected to the gate of the first transistor, and a gate of the fifth transistor is electrically connected to a first wiring;
- a first terminal of the sixth transistor is electrically connected to the sixth wiring, a second terminal of the sixth transistor is electrically connected to the gate of the first transistor, and a gate of the sixth transistor is electrically connected to the gate of the second transistor;
- a first terminal of the seventh transistor is electrically connected to the sixth wiring, a second terminal of the seventh transistor is electrically connected to the gate of the first transistor, and a gate of the seventh transistor is electrically connected to a second wiring;
- and
- a first terminal of the eighth transistor is electrically connected to the sixth wiring, a second terminal of the eighth transistor is electrically connected to the gate of the second transistor, and a gate of the eighth transistor is electrically connected to the first wiring,
- wherein a value of a ratio W/L of a channel width W to a channel length L of the first transistor is the highest among values of W/L of the first to eighth transistors.
A computer comprising:
- a main body including a keyboard and an LED lamp;
- and
- a housing including a display portion, the display portion including a pixel and a driver circuit,
- wherein the driver circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor;
- a first terminal of the first transistor is electrically connected to a fourth wiring, and a second terminal of the first transistor is electrically connected to a third wiring;
- a first terminal of the second transistor is electrically connected to a sixth wiring, and a second terminal of the second transistor is electrically connected to the third wiring;
- a first terminal of the third transistor is electrically connected to a seventh wiring, a second terminal of the third transistor is electrically connected to a gate of the second transistor, and a gate of the third transistor is electrically connected to the seventh wiring;
- a first terminal of the fourth transistor is electrically connected to the sixth wiring, a second terminal of the fourth transistor is electrically connected to the gate of the second transistor, and a gate of the fourth transistor is electrically connected to a gate of the first transistor;
- a first terminal of the fifth transistor is electrically connected to a fifth wiring, a second terminal of the fifth transistor is electrically connected to the gate of the first transistor, and a gate of the fifth transistor is electrically connected to a first wiring;
- a first terminal of the sixth transistor is electrically connected to the sixth wiring, a second terminal of the sixth transistor is electrically connected to the gate of the first transistor, and a gate of the sixth transistor is electrically connected to the gate of the second transistor;
- a first terminal of the seventh transistor is electrically connected to the sixth wiring, a second terminal of the seventh transistor is electrically connected to the gate of the first transistor, and a gate of the seventh transistor is electrically connected to a second wiring;
- and
- a first terminal of the eighth transistor is electrically connected to the sixth wiring, a second terminal of the eighth transistor is electrically connected to the gate of the second transistor, and a gate of the eighth transistor is electrically connected to the first wiring,
- wherein a value of a ratio W/L of a channel width W to a channel length L of the first transistor is the highest among values of W/L of the first to eighth transistors.
Dependencies are inferred from the claim text.