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US 8,514,623 B2Granted
Method of maintaining the state of semiconductor memory having electrically floating body transistor
AssigneeZeno Semiconductor, Inc.
InventorsYuniarto Widjaja, Zvi Or-Bach
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Abstract
Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell.
Claims20
A semiconductor memory cell comprising:
- a floating body region configured to be charged to a level indicative of a state of the memory cell;
- a first region in electrical contact with said floating body region, located at a surface of said floating body region;
- and
- a second region in electrical contact with said floating body region, located below said floating body region, configured to inject charge into or extract charge out of said floating body region to maintain said state of the memory cell;
- wherein an amount of charge flow resulting from injecting charge into or extracting charge out of said floating body is determined by the state of the memory cell stored in said floating body region.
2 more elements
A semiconductor memory cell comprising:
- a floating body region;
- a first region in electrical contact with said floating body region;
- a second region in electrical contact with said floating body region and spaced apart from said first region;
- a gate positioned between said first and second regions;
- and
- a back-bias region;
- wherein applying a voltage to said back-bias region results in at least two stable floating body charge levels.
4 more elements
A semiconductor memory array comprising:
- a plurality of said memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell includes:
- a floating body region configured to be charged to a level indicative of a state of the memory cell;
- a first region in electrical contact with said floating body region;
- a second region in electrical contact with said floating body region and spaced apart from said first region;
- and
- a gate positioned between said first and second regions;
- and
- wherein a back-bias region is commonly connected to at least two of said memory cells, configured to inject charge into or extract charge out of said floating body region of each of said memory cells connected thereto, to maintain said state of the memory cells in parallel.
5 more elements
Dependencies are inferred from the claim text.