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US 8,514,622 B2Granted
Compact semiconductor memory device having reduced number of contacts, methods of operating and methods of making
AssigneeZeno Semiconductor, Inc.
InventorYuniarto Widjaja
Life of this patent
Estimating the term…
Abstract
An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The link or string includes at least one contact configured to electrically connect the memory cells to at least one control line, and the number of contacts in the string or link is the same as or less than the number of memory cells in the string or link.
Claims54
An integrated circuit comprising:
- a link or string of semiconductor memory cells, wherein each said memory cell comprises a floating body region for storing data;
- and
- said link or string comprises at least one contact configured to electrically connect said memory cells to at least one control line, wherein the number of contacts is the same as or less than the number of said memory cells.
An integrated circuit comprising:
- a plurality of contactless semiconductor memory cells, each said semiconductor memory cell comprising:
- a floating body region for storing data;
- first and second conductive regions interfacing with the floating body region;
- a gate;
- and
- an insulating region insulating said gate from said floating body region.
3 more elements
An integrated circuit comprising:
- a plurality of semiconductor memory cells connected in series, each said semiconductor memory cell comprising:
- a floating body region for storing data;
- first and second conductive regions interfacing with said floating body region;
- a gate;
- and
- an insulating region insulating the gate and the floating body region.
3 more elements
An integrated circuit comprising:
- a plurality of semiconductor memory cells connected in parallel, each said semiconductor memory cell comprising:
- a floating body region for storing data;
- a conductive region interfacing with the floating body region;
- a gate;
- and
- an insulating region insulating said gate from said floating substrate region;
- wherein at least one of said semiconductor memory cells is a contactless semiconductor memory cell.
4 more elements
An integrated circuit comprising:
- a plurality of contactless semiconductor memory cells connected in parallel, each said semiconductor memory cell comprising:
- a floating body region for storing data;
- first and second conductive regions interfacing with the floating body region;
- a gate;
- and
- an insulating region insulating the gate and the floating body region.
3 more elements
An integrated circuit comprising:
- a memory string or link comprising a set of contactless semiconductor memory cells;
- and
- a first contact contacting a semiconductor transistor forming part of said string or link;
- and
- wherein said contactless semiconductor memory cells are accessible via said first contact.
2 more elements
Dependencies are inferred from the claim text.