Method and mechanism for implementing PCB routing
AssigneeCadence Design Systems, Inc.
InventorsKen Wadland, Richard Allen Woodward, Jr., Randall Lawson, Alan G Strelzoff, David Tsai, Steve Russo
Life of this patent
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Abstract
A method and system for auto-routing wiring within a PCB. In some embodiment, a first broad region within a first layer and a counterpart first broad region within a second layer are defined. The counterpart regions define a first broad via location. In some embodiments, the first and second broad via locations of the first and second layers can then be subdivided into a plurality of triangular regions. The triangular regions on the first and second layers can then be compared to more accurately locate an appropriate via location.
Claims42
A computer implemented method for determining routing paths of an electronic circuit design, comprising:
- prior to initiating detail routing of the electronic circuit design, using at least one processor to perform at least a process, the process comprising:
- determining relative viability of channel routing, in which
- the channel routing routes a wire via a channel, which is on an edge shared between two of a plurality of rectangular tiles in a routing space, and
- the relative viability of channel routing indicates a likelihood of routing the wire to a plurality of first locations in the routing space through the channel;
- identifying a generalized routing path within at least one of the plurality of rectangular tiles based at least in part upon the relative viability of the channel routing;
- and
- identifying a location of a via in a plurality of triangular regions of the at least one of the plurality of rectangular tiles in a layer based at least in part upon the channel data and the generalized routing path by performing wavefront expansion and creating a probe from a face to a neighboring face of the face in the plurality of triangular regions during the wavefront expansion, wherein the action of identifying the location of the via comprises:
- determining a first via location in the layer for the via;
- and
- determining the location for the via in the layer based at least in part upon the first via location prior to initiating the detail routing.
A computer program product comprising a non-transitory computer-usable storage medium having executable code which, when executed by a processor, causes the processor to execute a process for determining routing paths, the process comprising:
- prior to initiating detail routing of the electronic circuit design, using at least one processor to perform at least a process, the process comprising:
- determining relative viability of channel routing, in which the channel routing routes a wire via a channel which is on an edge shared between two of a plurality of rectangular tiles in a routing space, and the relative viability of channel routing indicates a likelihood of routing the wire to a plurality of first locations in the routing space through the channel;
- identifying a generalized routing path within at least one of the plurality of rectangular tiles based at least in part upon the relative viability of the channel routing;
- and
- identifying a location of a via in a plurality of triangular regions of the at least one of the plurality of rectangular tiles in a layer based at least in part upon the channel data and the generalized routing path by performing wavefront expansion and creating a probe from a face to a neighboring face of the face in the plurality of triangular regions during the wavefront expansion, wherein the action of identifying the location of the via comprises:
- determining a first via location in the layer for the via;
- and
- determining the location for the via in the layer based at least in part upon the first via location prior to initiating the detail routing.
A computer system, comprising:
- at least one processor, prior to initiating detail routing of the electronic circuit design, that is to:
- determine relative viability of channel routing, in which the channel routing routes a wire via a channel which is on an edge shared between two of a plurality of rectangular tiles in a routing space, wherein the relative viability of channel routing indicates a likelihood of routing the wire to a plurality of first locations in a routing space through the channel;
- identify a generalized routing path within at least one of the plurality of rectangular tiles based at least in part upon the relative viability of the channel routing;
- and
- identify a location of a via in a plurality of triangular regions of the at least one of the plurality of rectangular tiles in a layer based at least in part upon the channel data and the generalized routing path by performing wavefront expansion and creating a probe from a face to a neighboring face of the face in the plurality of triangular regions during the wavefront expansion, wherein the at least one processor that is to identify the location of the via is further to:
- determine a first via location in the layer for the via;
- and
- determine the location for the via in the layer based at least in part upon the first via location prior to initiating the detail routing.
Dependencies are inferred from the claim text.