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US 8,510,701 B2Granted
Over stress verify design rule check
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChen-Ting Ko, Chih-Hsien Chang, Yung-Chow Peng
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Abstract
Some aspects of this disclosure provide for electronic design automation (EDA) techniques that check whether individual blocks, such as transistors or other semiconductor devices, are connected to their correct power domains during design. In this way, the disclosed EDA techniques can limit or prevent overstress conditions applied to blocks and help to improve reliability of integrated circuits, when manufactured.
Claims11
An EDA tool, comprising:
- memory to store a structural representation of an integrated circuit, the structural representation comprising:
- a plurality of blocks labeled with respective operating voltages, and a supply node labeled with a supply voltage coupled to one or more of the plurality of blocks;
- and
- an analysis module configured to calculate a voltage difference between the supply voltage and an operating voltage with which a block is labeled, and further configured to compare the calculated voltage difference to a predetermined voltage range disposed about the supply voltage.
1 more element
Dependencies are inferred from the claim text.