Method and apparatus for camouflaging a standard cell based integrated circuit with micro circuits and post processing

An application specific integrated circuit (ASIC) having a plurality of interconnected functional logic cells that together perform one or more ASIC logical functions and camouflaging, the camouflaging defined by performing steps comprising:

• identifying at least one gap between the plurality of interconnected functional logic cells having no functional logic therein;
• placing one filler cell or combination of filler cells into the identified gap, wherein at least one of the filler cells has a physical design layout similar to but different from at least one of the functional logical cells;
• and
• defining a routing of the placed one filler cell or combination of filler cells;
• wherein the filler cell or routed combination of filler cells camouflages the interconnected functional logic cells and the routed one or more filler cells together perform at least one camouflage logical function reproducing at least one of the ASIC logical functions but do not interfere with any of the ASIC logical functions.

An application specific integrated circuit (ASIC), comprising:

• a plurality of interconnected functional logic cells, together performing one or more ASIC logical functions;
• one or more filler cells disposed into a gap between the plurality of interconnected functional logic cells, wherein the filler cells comprise a physical layout similar to, but different than at least one of the interconnected functional logic cells;
• and
• a routing of the one or more filler cells;
• wherein the filler cell or routed combination of filler cells camouflages the interconnected functional logic cells and the routed one or more filler cells together perform at least one camouflage logical function reproducing at least one of the ASIC logical functions but do not interfere with any of the ASIC logical functions.

A computer-implemented method of camouflaging an application specific integrated circuit (ASIC), wherein the ASIC comprises a plurality of interconnected functional logic cells selected from a cell library having a plurality of library cells that together perform one or more ASIC logical functions, the method comprising the steps of:

• identifying, using the computer, at least one gap between the plurality of interconnected functional logic cells having no functional logic therein;
• placing, using the computer, a combination of filler cells into the identified gap, wherein a first cell of the combination of filler cells has a first physical design layout modified from that of a corresponding first library cell to perform no logical function, a second cell of the combination of filler cells has a second physical design layout modified from that of a corresponding second library cell to perform a modified logical function, and a third cell of the combination of filler cells has a third physical design layout unmodified from a corresponding third library cell;
• and
• defining, using the computer, a routing of the placed one filler cell or combination of filler cells;
• wherein the routed combination of filler cells camouflages the interconnected functional logic cells and the combination of filler cells together reproduce at least one of the ASIC logical functions but do not interfere with any of the ASIC logical functions.

An application specific integrated circuit (ASIC) having a plurality of interconnected functional logic cells selected from a cell library having a plurality of library cells that together perform one or more ASIC logical functions and camouflaging, the camouflaging defined by performing steps comprising:

• identifying at least one gap between the plurality of interconnected functional logic cells having no functional logic therein;
• placing, using the computer, a combination of filler cells into the identified gap, wherein a first cell of the combination of filler cells has a first physical design layout modified from that of a corresponding first library cell to perform no logical function, a second cell of the combination of filler cells has a second physical design layout modified from that of a corresponding second library cell to perform a modified logical function, and a third cell of the combination of filler cells has a third physical design layout unmodified from a corresponding third library cell;
• and
• defining a routing of the placed one filler cell or combination of filler cells;
• wherein the routed combination of filler cells camouflages the interconnected functional logic cells and the combination of filler cells together reproduce at least one of the ASIC logical functions but do not interfere with any of the ASIC logical functions.

An application specific integrated circuit (ASIC), comprising:

• a plurality of interconnected functional logic cells, together performing one or more ASIC logical functions;
• a plurality of filler cells disposed into a gap between the plurality of interconnected functional logic cells, wherein the plurality of filler cells comprises:
• a first one of the plurality of filler cells having a first physical design layout modified from that of a corresponding first library cell to perform no logical function;
• a second one of the plurality of filler cells having a second physical design layout modified from that of a corresponding second library cell to perform a modified logical function;
• and
• a third one of the plurality of filler cells has a third physical design layout unmodified from a corresponding third library cell;
• and
• a routing of the plurality of filler cells;
• wherein the routed plurality of filler cells camouflages the interconnected functional logic cells and together reproduce at least one of the ASIC logical functions but do not interfere with any of the ASIC logical functions.