System and method for modeling I/O simultaneous switching noise
AssigneeInternational Business Machines Corporation
InventorsErik Breiland, Charles S. Chiu, Prince George
Life of this patent
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Abstract
The invention generally relates to systems and methods for modeling I/O simultaneous switching noise, and, more particularly, to systems and methods for modeling I/O simultaneous switching noise in a selected chip window area while accounting for the effect of current sharing among neighbors. A method includes determining a current sharing factor of areas of an integrated circuit (IC) chip package, and determining an offload scaling factor of the IC chip package based upon the current sharing factor and numbers of I/O devices in neighboring areas of the IC chip package.
Claims20
A method for improving simultaneous switching output (SSO) noise analysis, comprising:
- determining, by a processor, a current sharing factor of adjacent areas of an integrated circuit (IC) chip package based upon package inductance, on chip power bus resistance, on chip power bus capacitance, and rise time of actual I/O devices of the IC chip package, wherein the current sharing factor is a ratio of voltage compression between the adjacent areas of the IC chip package;
- and
- determining an offload scaling factor of the IC chip package based upon the determined current sharing factor for the adjacent areas of the IC chip package and the actual I/O devices in the adjacent areas of the IC chip package, to perform the SSO noise analysis,
- wherein the determining the offload scaling factor includes determining a number of equivalent I/O devices in a first area of the adjacent areas of the IC chip package having a highest number of the actual I/O devices in comparison to a number of the actual I/O devices in at least one second area of the adjacent areas of the IC chip package that is adjacent to the first area having the highest number of the actual I/O devices,
- wherein the offload scaling factor is a ratio of the number of the equivalent I/O devices in the first area to the highest number of the actual I/O devices in the first area;
- and
- wherein the adjacent areas of the IC chip package are modeling windows.
A method for performing a simultaneous switching output (SSO) noise analysis, comprising:
- providing a computer infrastructure that is structured and arranged to:
- determine a current sharing factor of adjacent areas of an integrated circuit (IC) chip package based upon package inductance, on chip power bus resistance, on chip power bus capacitance, and rise time of actual I/O devices of the IC chip package, wherein the current sharing factor is a ratio of voltage compression between the adjacent areas of the IC chip package;
- and
- determine an offload scaling factor of the IC chip package based upon the determined current sharing factor for the adjacent areas of the IC chip package and the actual I/O devices in the adjacent areas of the IC chip package, to perform the SSO noise analysis,
- wherein the determining the offload scaling factor includes determining a number of equivalent I/O devices in a first area of the adjacent areas of the IC chip package having a highest number of the actual I/O devices in comparison to a number of the actual I/O devices in at least one second area of the adjacent areas of the IC chip package that is adjacent to the first area having the highest number of the actual I/O devices,
- wherein the offload scaling factor is a ratio of the number of the equivalent I/O devices in the first area to the highest number of the actual I/O devices in the first area and
- wherein the adjacent areas of the IC chip package are modeling windows.
A computer program product comprising a tangible computer usable storage memory having a computer readable program embodied in the tangible computer usable storage memory, wherein the computer readable program when executed on a computing device is operable to cause the computing device to:
- determine a current sharing factor of adjacent areas of an integrated circuit (IC) chip package based upon package inductance, on chip power bus resistance, on chip power bus capacitance, and rise time of actual I/O devices of the IC chip package, wherein the current sharing factor is a ratio of voltage compression between the adjacent areas of the IC chip package;
- and
- determine an offload scaling factor of the IC chip package based upon the determined current sharing factor for the adjacent areas of the IC chip package and the actual I/O devices in the adjacent areas of the IC chip package, to perform an SSO noise analysis,
- wherein the determining the offload scaling factor includes determining a number of equivalent I/O devices in a first area of the adjacent areas of the IC chip package having a highest number of the actual I/O devices in comparison a number of the actual I/O devices in at least one second area of the adjacent area of the IC chip package that is adjacent to the first area of the having the highest number of the actual I/O devices
- wherein the offload scaling factor is a ratio of the number of the equivalent I/O devices in the first area to the highest number of the actual I/O devices in the first area;
- and
- wherein the adjacent areas of the IC chip package are modeling windows.
Dependencies are inferred from the claim text.