Ordering of statistical correlated quantities

A computer system comprising:

• a set of computing devices configured to determine an order of statistical correlated quantities in an integrated circuit, by performing actions comprising:
• receiving timing quantity data derived from testing of an integrated circuit, the timing quantity data including a set of timing quantities associated with a plurality of paths in the integrated circuit;
• determining a most critical timing quantity in the set of timing quantities,
• wherein the determining of the most critical timing quantity is performed using a Monte Carlo analysis of N timing quantities and M Monte Carlo Trials;
• forming a tiered timing quantity arrangement for ordering a plurality of timing quantities in the set of timing quantities;
• removing the most critical timing quantity from the set of timing quantities and placing the most critical timing quantity in an uppermost available tier of the tiered timing quantity arrangement;
• and
• repeating the determining, forming and removing for the set of timing quantities excluding the removed most critical timing quantity.

A program product stored on a non-transitory computer readable medium for determining an order of statistical correlated quantities in an integrated circuit, which when executed on at least one computing device, performs the following:

• receives timing quantity data derived from testing of an integrated circuit, the timing quantity data including a set of timing quantities associated with a plurality of paths in the integrated circuit;
• determines a most critical timing quantity in the set of timing quantities;
• forms a tiered timing quantity arrangement for ordering a plurality of timing quantities in the set of timing quantities;
• removes the most critical timing quantity from the set of timing quantities and placing the most critical timing quantity in an uppermost available tier of the tiered timing quantity arrangement;
• repeats the receiving, determining, forming and removing for the set of timing quantities excluding the removed most critical timing quantity;
• and
• modifies a design of the integrated circuit to reduce a criticality of the most critical timing quantity.