Techniques for electromigration stress determination in interconnects of an integrated circuit
AssigneeFreescale Semiconductor, Inc.
InventorsErtugrul Demircan, Mehul D. Shroff
Life of this patent
Estimating the term…
Abstract
A technique for determining stress in interconnects of an integrated circuit design includes generating a maximal spanning tree of a directed graph. The directed graph represents an interconnect of an integrated circuit design. The technique also includes locating a first point on the spanning tree that has a lowest stress and a second point on the spanning tree that has a highest stress. The technique further includes determining whether a maximum first stress between the first and second points is less than a critical stress.
Claims20
A method of determining stress in interconnects of an integrated circuit design, comprising:
- generating, using a data processing system, a maximal spanning tree of a directed graph, wherein the directed graph represents an interconnect network of an integrated circuit design;
- locating, using the data processing system, a first point on the spanning tree having a lowest stress and a second point on the spanning tree having a highest stress;
- and
- determining, using the data processing system, whether a maximum first stress between the first and second points is less than a critical stress.
A data processing system for determining stress in interconnects of an integrated circuit design, the data processing system comprising:
- a storage subsystem;
- and
- a processor coupled to the storage subsystem, wherein the processor is configured to generate a maximal spanning tree of a directed graph that represents an interconnect of an integrated circuit design, locate a first point on the spanning tree having a lowest stress and a second point on the spanning tree having a highest stress, and determine whether a maximum first stress between the first and second points is less than a critical stress.
A method of determining stress in interconnects of an integrated circuit design, comprising:
- generating, using a data processing system, a maximal spanning tree of a directed graph, wherein the directed graph represents an interconnect network of an integrated circuit design;
- locating, using the data processing system, a first point on the spanning tree having a lowest stress and a second point on the spanning tree having a highest stress;
- determining, using the data processing system, whether a maximum first stress between the first and second points is less than a critical stress;
- indicating, using the data processing system, a pass condition in response to the maximum first stress being less than the critical stress, wherein the maximum first stress is given by:
- Δσ
- ij
- =
- c
- R
- sh
- ×
- Δ
-
-
- V
- ij
- where ‘c’ is a material-dependent constant, Rsh is the sheet resistance, and ΔVij is the potential from node ‘i ‘to node ‘j’, and wherein the lowest stress occurs at a highest potential and the highest stress occurs at a lowest potential.
Dependencies are inferred from the claim text.