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US 8,510,641 B2Granted
Circuit and technique for reducing parity bit-widths for check bit and syndrome generation for data blocks through the use of additional check bits to increase the number of minimum weighted codes in the hamming code H-matrix
AssigneeInvensas Corporation
InventorOscar Frederick Jones, Jr.
Life of this patent
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Abstract
A technique for reducing parity bit-widths for check bit and syndrome generation through the use of additional check bits to increase the number of minimum weighted codes in the Hamming Code H-Matrix. The technique of the present invention may be implemented while adding no additional correction/detection capability, in order to reduce the number of data bits that are used for each check bit/syndrome generation and to reduce the width of the parity generating circuitry.
Claims5
An ECC circuit for selecting parity bit-widths comprising:
- circuitry for establishing a minimum first number of check bits required for generation of check bits and syndromes for a desired Hamming distance based upon said first number of check bits;
- circuitry for adding at least one additional check bit to said first number of check bits to provide a second number of said check bits and increase a number of low weighted Hamming codes;
- and
- circuitry for reducing the width of a parity generating circuit in response to said second number of check bits.
1 more element
Dependencies are inferred from the claim text.