Semiconductor storage device and method of operating the same

An operation method of a semiconductor storage device including a plurality of data cells for storing error correction codes, each of which comprises of symbols, each of which comprises bits, and which codes allow error correction in units of symbols, a plurality of reference cells used for reading from said data cells, and a peripheral circuit comprising an ECC circuit,

• wherein each of said plurality of data cells and said plurality of reference cells includes any of a phase change resistance element, a metal oxide resistance element and a solid electrolyte resistance element,
• wherein the respective symbols are read by using different reference cells,
• wherein, when a correctable error is detected in read data from data cells, for a first error symbol of a one-bit error pattern, said peripheral circuit compares respective bits of the read data with corresponding bits of decoded data outputted by the ECC circuit and corrects a data cell corresponding to a non-matching bit, that is, an error bit, and for a second error symbol of a multi-bit error pattern, said peripheral circuit corrects a reference cell used for reading the second error symbol,
• wherein, after the data cell associated with the error bit included in the first error symbol is corrected, a re-reading operation and an error detecting operation are performed for the data cells forming said error correction codes, and
• wherein, when a correctable error is detected again in the same symbol as the first error symbol within the re-read data, said peripheral circuit performs an operation for correcting a reference cell used for reading of said first error symbol.

An operation method of a semiconductor storage device which comprises data cells which store first to m-th block codes as error correction codes which allow error correction in units of symbols, first to nth reference cells, and a peripheral circuit containing first to mth ECC circuits, each of the error correction codes comprising a plurality of symbols, each of which comprises a plurality of bits,

• wherein each of said plurality of data cells and said first to nth reference cells includes any of a phase change resistance element, a metal oxide resistance element and a solid electrolyte resistance element,
• wherein data of the first to mth block codes are read out, while using an ith reference cell of the first to nth reference cells, when an ith symbol of each of the first to mth block codes is read, and error detection is carried cut on each of the first to mth block codes by using the first to mth ECC circuits, respectively, and
• wherein, in a case where any of said first to mth ECC circuits detects a correctable error, for the m ith symbols read by using said ith reference cell, said peripheral circuit corrects a data in a data cell corresponding to an error bit when an error is detected in one of the ith symbols, and said peripheral circuit corrects a data said ith reference cell when errors are detected in two or more of the ith symbols,
• wherein, in the case where any of said first to mth ECC circuits detects the correctable error, for the m ith symbols read by using said ith reference cell, said peripheral circuit performs an operation of comparing respective bits of the ith symbol in a kth block code with corresponding bits of an ith symbol in decoded data outputted from the kth ECC circuit and corrects a data cell of a non-matching bit, that is, an error bit, when an error is detected in one of the ith symbols, that is, an error symbol is detected only for the ith symbol in the kth block code, and performs an operation of correcting data in the ith reference cell when errors are detected in two or more of the ith symbols.

A semiconductor storage device which uses, for error detection and error correction, error correction codes each of which comprises of symbols, each of which comprises bits, and which codes allow error correction in units of symbols, comprising:

• a plurality of memory cells each including any of a phase change resistance element, a metal oxide resistance element and a solid electrolyte resistance element;
• and
• a peripheral circuit,
• wherein said plurality of memory cells include:
• data cells used for storing said plurality of symbols;
• and
• reference cells used for reading said plurality of symbols,
• wherein said peripheral circuit is configured to read said respective symbols by using different reference cells,
• wherein, when a correctable error is detected in read data from data cells forming said error correction codes and corresponding to an input address, (A) for a first error symbol of a one-bit error pattern, said peripheral circuit corrects data of a data cell corresponding to the error bit, and (B) for a second error symbol of a multi-bit error pattern, said peripheral circuit corrects data in a reference cell used for reading the second error symbol,
• wherein after the data in the data cell associated with the first error symbol described in said (A) is corrected, a re-reading operation and an error detecting operation are performed for the data cells forming said error correction codes, and
• when a correctable error is detected again in the re-read data, (C) a data in a reference cell used to read said first error symbol is corrected.

A semiconductor storage device which uses, for error detection and error correction, error correction codes each of which comprises of symbols, each of which comprises bits, and which codes allow error correction in units of symbols, comprising:

• a plurality of memory cells each including any of a phase change resistance element, a metal oxide resistance element and a solid electrolyte resistance element;
• and
• a peripheral circuit including an ECC circuit,
• wherein said plurality of memory cells include:
• data cells used for storing said plurality of symbols;
• and
• reference cells used for reading said plurality of symbols,
• wherein said peripheral circuit reads said respective symbols by using different reference cells, and
• wherein, when a correctable error is detected in read data from data cells, for a first error symbol of a one-bit error pattern, said peripheral circuit performs a control of comparing respective bits of the read data with corresponding bits of decoded data outputted by said ECC circuit and correcting a data cell corresponding to a non-matching bit, that is, an error bit, and for a second error symbol of a multi-bit error pattern, said peripheral circuit performs a control for correcting a reference cell used for reading the second error symbol,
• wherein, after the data cell associated with the error bit included in the first error symbol is corrected, a re-reading operation and an error detecting operation are performed for the data cells forming said error correction codes, and
• wherein, when a correctable error is detected again in the same symbol as the first error symbol within the re-read data, said peripheral circuit performs an operation for correcting a reference cell used for reading of said first error symbol.

A semiconductor storage device, comprising:

• a plurality of memory cells storing first to mth block codes which are error correction codes each of which comprises of a plurality of symbols, each of which comprises a plurality of bits, the error correction codes allowing error correction in units of symbols;
• first to nth reference cells;
• and a peripheral circuit including first to mth ECC circuits, wherein said peripheral circuit is configured to read said first to mth block codes while using an ith reference cell of the first to nth reference cells, when an ith symbol of each of the first to mth block codes is read, and to perform error detection on each of the first to mth block codes by using said first to mth ECC circuits, respectively, and wherein, in a case where any of said first to mth ECC circuits detects a correctable error, for the m ith symbols read by using said ith reference cell, said peripheral circuit corrects a data in a data cell corresponding to an error bit when an error is detected in one of the ith symbols, and said peripheral circuit corrects a data said ith reference cell when errors are detected in two or more of the ith symbols,
• wherein, in the case where any of said first to mth ECC circuits detects the correctable error, for the m ith symbols read by using said ith reference cell, said peripheral circuit performs an operation of comparing respective bits of the ith symbol in a kth block code with corresponding bits of am an ith symbol in decoded data outputted from the kth ECC circuit and corrects a data cell of a non-matching bit, that is, an error bit, when an error is detected in one of the ith symbols, that is, an error symbol is detected only for the ith symbol in the kth block code, and performs an operation of correcting data in the ith reference cell when errors are detected in two or more of the ith symbols.