Control method for a semiconductor memory device
AssigneeElpida Memory, Inc.
InventorTetsuya Arai
Life of this patent
Estimating the term…
Abstract
To provide a memory array for information bit that stores information bits, a memory array for check bit that stores check bits, a correction circuit that, in response to a write request, reads the information bit and the check bit corresponding to a write address from the respective memory arrays and corrects an error included in the information bit, and a mixer temporarily holding information bit corrected by the correction circuit. The mixer overwrites only a part of bytes of the held information bits with write data according to a byte mask signal. Accordingly, a capacity required for the memory array for check bit can be reduced while the byte mask function is maintained.
Claims14
A method comprising:
- reading first data from a memory array in response to a write request, the write request including second data that is to be written into the memory array and a mask information that designates a part of the second data to be masked;
- performing an error correction on the first data to produce a third data;
- overwriting a portion of the third data with a remaining part of the second data to produce fourth data;
- writing the fourth data into the memory array;
- coding the fourth data to produce fifth data;
- and
- writing the fifth data into the memory array.
Dependencies are inferred from the claim text.