Back to results
US 8,510,630 B2Granted
Nibble encoding for improved reliability of non-volatile memory
AssigneeIntel Corporation
InventorChristopher J. Bueb
Life of this patent
Estimating the term…
Abstract
A wireless device to include a non-volatile memory to execute an encoding scheme to provide single-cell error detection and correction on program operations in which the initial nibble value is Fh and on program operations that result in a nibble value of 0h. The non-volatile memory uses multiple writes to program a nibble more than once with non-zero data between erase cycles.
Claims20
An apparatus comprising:
- a multicore processor;
- and
- a non-volatile memory device having a plurality of multilevel memory cells and an encoder controller to:
- choose a set of first-write nibble codes for an encoding scheme so that no more than one level value stored in a multilevel memory cell of a given nibble code can match a level value in corresponding multilevel memory cells of other nibble codes included in the set of first-write nibble codes and a subset of the set of first-write nibble codes are rewritable to multiple different non-zero nibble codes;
- and
- use the encoding scheme to provide first-write error protection to a four-bit boundary on the non-volatile memory device.
3 more elements
A method comprising:
- choosing, at an encoder controller for a non-volatile memory device, a set of first-write nibble codes for an encoding scheme, the set chosen so that no more than one level value stored in a multilevel memory cell of a given nibble code can match a level value in corresponding multilevel memory cells of other nibble codes included in the set and a subset of the set of first-write nibble codes are rewritable to multiple different non-zero nibble codes;
- and
- using the encoding scheme to provide first-write error protection to a four-bit boundary on the non-volatile memory device.
A system comprising:
- a wireless interface having an antenna;
- a multicore processor;
- and
- a non-volatile memory having multilevel memory cells and an encoder controller to provide first-write error protection to a four-bit boundary for first-write nibble codes programmed to the multilevel memory cells, each of the multilevel memory cells placeable into any of more than two charge states, each first-write nibble code including four code cells, each code cell corresponding to a multilevel memory cell and comprising a level value included in a set of more than two level values corresponding to the more than two charge states, each level value in the set of more than two level values corresponding to one of the more than two charge states.
1 more element
Dependencies are inferred from the claim text.