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US 8,510,616 B2Granted
Scalable scan-based test architecture with reduced test time and test power
AssigneeNVIDIA Corporation
InventorRakshit Kumar Singhal
Life of this patent
Estimating the term…
Abstract
A scalable scan-based architecture with reduced test time, test power and test pin-count in scan based testing of ICs. In an embodiment, a test vector is scanned serially into a functional memory element at a first frequency, which then de-multiplexes the bits in the test vector to multiple sub-chains at a lower frequency. Due to the use of lower frequency to scan-in, the power dissipation is reduced. Due to the use of the higher frequency to scan-in the test vector as well as multiple sub-chains, the test time is reduced. Due to the use of the functional memory elements for scanning in the test vector at higher frequency, any number of chains can potentially be supported.
Claims18
A circuit comprising:
- a first sub-chain containing a first sequence of functional memory elements;
- a second sub-chain containing a second sequence of functional memory elements;
- a scan splitter block comprises a first functional memory element, said scan splitter block operable to receive a test vector containing a sequence of bits at a first frequency and to de-multiplex said sequence of bits such that a first subset of bits is sent to said first sub-chain and a second subset of bits is sent to said second sub-chain at a second frequency and a third frequency respectively in a scan mode, said first subset of bits and said second subset of bits being contained in said sequence of bits, wherein said scan splitter block is operable to capture results from said first sub-chain and said second sub-chain and output said results at said first frequency;
- and
- a combinational logic to receive at least one input from said first sub-chain and said second sub-chain and to generate an output bit in a functional test mode, wherein said first frequency is greater than each of said second frequency and said third frequency, wherein said first sequence of functional memory elements, said second sequence of functional memory elements, and said first functional memory element are contained in a functional portion of said circuit.
2 more elements
An integrated circuit comprising:
- means for receiving a test vector containing a sequence of bits at first frequency using at least one functional memory element;
- means for de-multiplexing said test vector into a plurality of sub-chains in the form of a corresponding number of sub-vectors, each sub-chain containing a corresponding set of functional memory elements connected in series, wherein each sub-vector is scanned into said corresponding sub-chain at a frequency lower than said first frequency, and wherein each sub-vector is scanned into said corresponding sub-chain in alternative clock cycles;
- means for performing a functional test on a combinational logic contained in said integrated circuit after said de-multiplexing;
- means for capturing in said plurality of sub-chains said results generated by said combinational logic in said functional test;
- means for examining said results to determine whether said integrated circuit operates according to a desired specification, wherein said sets of functional memory elements and said at least one functional memory element together form a functional portion of said integrated circuit;
- means for multiplexing the results captured by said plurality of sub-chains to form a single serial output stream;
- and
- means for outputting said single serial output stream at said first frequency.
5 more elements
A method of testing an integrated circuit, said method comprising:
- receiving a test vector containing a sequence of bits at first frequency using at least one functional memory element;
- de-multiplexing said test vector into a plurality of sub-chains in the form of a corresponding number of sub-vectors, each sub-chain containing a corresponding set of functional memory elements connected in series, wherein each sub-vector is scanned into said corresponding sub-chain at a frequency lower than said first frequency, and wherein each sub-vector is scanned into said corresponding sub-chain in alternative clock cycles;
- performing a functional test on a combinational logic contained in said integrated circuit after said de-multiplexing;
- capturing in said plurality of sub-chains said results generated by said combinational logic in said functional test;
- examining said results to determine whether said integrated circuit operates according to a desired specification, wherein said sets of functional memory elements and said at least one functional memory element together form a functional portion of said integrated circuit;
- multiplexing said results captured by said plurality of sub-chains to form a single serial output stream;
- and
- sending said single output stream at said first frequency to a test equipment.
5 more elements
Dependencies are inferred from the claim text.