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US 8,510,612 B2Granted
Disabling outbound drivers for a last memory buffer on a memory channel
AssigneeIntel Corporation
InventorsPete D. Vogt, Dennis W. Brzezinski, Warren R. Morrow
Life of this patent
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Abstract
Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface.
Claims9
An integrated circuit to provide a memory buffer to isolate one or more dynamic random access memory devices (DRAM devices) from a point-to-point channel, the integrated circuit comprising:
- an inbound redrive circuit to receive and redrive signals on an inbound path of the point-to-point channel, the inbound redrive circuit including, at least in part, two or more bit-lanes for the inbound path of the point-to-point channel;
- an outbound redrive circuit to receive and redrive signals on an outband path of the point-to-point channel, the outbound redrive circuit including, at least in part, two or more bit-lanes for the outbound path of the point-to-point channel;
- a pattern generator coupled with the inbound redrive circuit, the pattern generator to provide a permuting alert pattern, wherein the permuting alert pattern is generated by a 12-bit linear-feedback shift register (LFSR) with a polynomial of x12+x7+x4+x3+1;
- and
- a double data rate (DDR) memory interface to couple the memory buffer with the one or more DRAM devices, the memory interface to receive data from the outbound redrive circuit and to send data to the inbound redrive circuit.
2 more elements
A system comprising:
- a host;
- and
- an integrated circuit coupled with the host, the integrated circuit to provide a memory buffer to isolate one or more dynamic random access memory devices (DRAM devices) from a point-to-point channel, the integrated circuit including,
- an inbound redrive circuit to receive and redrive signals on an inbound path of the point-to-point channel, the inbound redrive circuit including, at least in part, two or more bit-lanes for the inbound path of the point-to-point channel,
- an outbound redrive circuit to receive and redrive signals on an outbound path of the point-to-point channel, the outbound redrive circuit including, at least in part, two or more bit-lanes for the outbound path of the point-to-point channel,
- a pattern generator coupled with the inbound redrive circuit, the pattern generator to provide a permuting alert pattern, wherein the permuting alert pattern is generated by a 12-bit linear-feedback shift register (LFSR) with a polynomial of x12+x7+x4+x3+1, and
- a double data rate (DDR) memory interface to couple the memory buffer with the one or more DRAM devices, the memory interface to receive data from the outbound redrive circuit and to send data to the inbound redrive circuit.
4 more elements
Dependencies are inferred from the claim text.