Apparatus and method using first and second clocks

An apparatus, comprising:

• a first input configured to receive a first signal representing a frequency ratio of a first clock and a second clock, the second clock having a higher frequency than the first clock;
• a first output configured to provide a second signal representing a number of clock pulses of the second clock occurring between a first clock pulse and a second clock pulse of the first clock;
• a second output configured to provide a third signal representing a time offset between (1) a clock pulse of the second clock that occurs between the second clock pulse and a third clock pulse of the first clock, and (2) the second clock pulse of the first clock wherein the ratio of the first clock and the second clock is represented by a first bit sequence;
• a first adder;
• a register arranged in series with the first adder;
• a feedback loop coupling the register to the first adder;
• and
• a first discarding unit, wherein the first adder is configured to add the ratio of the first clock and the second clock with a value received by the feedback loop and to output a second bit sequence, and the first discarding unit is configured to generate a third bit sequence by discarding at least one of the bits of the second bit sequence.

A method, comprising:

• receiving an indication of a ratio of a frequency of a first clock and a second clock;
• generating an indication of a number of clock pulses of the second clock occurring between a first clock pulse and a second clock pulse of the first clock;
• generating an indication of a time offset between (1) a clock pulse of the second clock, which occurs between the second clock pulse and a third clock pulse of the first clock, and (2) the second clock pulse of the first clock, wherein the number of clock pulses of the second clock occurring between a first clock pulse and a second clock pulse of the first clock depends on the time offset;
• and
• providing the indication of time offset to a digital filter having a first stage configured to operate at the first clock and a second stage configured to operate at the second clock.