US 8,510,588 B2 · Clock generation circuit and semiconductor device including the same

Abstract

Objects of the invention are to provide a clock generation circuit and to provide a semiconductor device including the clock generation circuit. The clock generation circuit includes an edge detection circuit, a reference clock generation circuit, a reference clock counter circuit, and a frequency-divider circuit. The reference clock counter circuit is a circuit which outputs a counter value, which is obtained by counting the number of waves of a reference clock signal outputted from the reference clock generation circuit, in a period of time from when the edge detection circuit detects an edge of a signal which is externally inputted to the edge detection circuit to when the edge detection circuit detects the next edge, to the frequency-divider circuit. The frequency-divider circuit is a circuit which frequency-divides the reference clock signal based on the counter value.

Claims21

Dependent claims

A semiconductor device comprising:

a power supply circuit comprising a regulator;
a first circuit configured to receive a first clock signal and a first signal and output a second signal;
and
a second circuit configured to receive the second signal and output a second clock signal,
wherein the power supply circuit is configured to supply a power supply voltage regulated by the regulator to the first circuit and the second circuit,
wherein the first circuit is configured to increment a value of the second signal in accordance with the first clock signal,
wherein the first circuit is configured to reset the value of the second signal in accordance with the first signal,
wherein the second circuit is configured to generate the second clock signal,
wherein a cycle of the second clock signal corresponds to a period while the value of the second signal grows by a value, and
wherein a first cycle of the second clock signal in a first period is longer than a second cycle of the second clock signal in a second period.

7 more elements

A semiconductor device comprising:

an antenna configured to receive a wireless signal and generate an electromotive force from the wireless signal;
a first power supply circuit configured to generate a first power supply voltage by regulating the electromotive force,
a second power supply circuit configured to generate a second power supply voltage from the electromotive force,
a first circuit configured to receive a first clock signal and a first signal and output a second signal;
a second circuit configured to receive the second signal and output a second clock signal;
and
a third circuit configured to operate using the second clock signal,
wherein the first power supply circuit is configured to supply the first power supply voltage to the first circuit and the second circuit,
wherein the second power supply circuit is configured to supply the second power supply voltage to the third circuit,
wherein the first circuit is configured to increment a value of the second signal in accordance with the first clock signal,
wherein the first circuit is configured to reset the value of the second signal in accordance with the first signal,
wherein the second circuit is configured to generate the second clock signal,
wherein a cycle of the second clock signal corresponds to a period while the value of the second signal grows by a value, and
wherein a first cycle of the second clock signal in a first period is longer than a second cycle of the second clock signal in a second period.

11 more elements

Dependencies are inferred from the claim text.

Clock generation circuit and semiconductor device including the same

Life of this patent

Clock generation circuit and semiconductor device including the same

Life of this patent

Abstract

Claims21