Asynchronous sleep mode for host controller
AssigneeIntel Corporation
InventorsChoon Gun Por, Karthi R. Vadivelu
Life of this patent
Estimating the term…
Abstract
Embodiments of the invention utilize a universal serial bus (USB) host controller to traverse an asynchronous data transfer list to identify data transfers to execute. The asynchronous data transfer list may include a plurality of header nodes, each header node to identify data transfers to one of a plurality of devices operatively coupled to an electronic device. The USB host controller may execute an extended sleep mode in response to identifying no data transfers to execute and receiving an indication that the system processor is in a sleep state. The USB host controller may exit the extended sleep mode in response to receiving an indication that the processor is in non-sleep state.
Claims16
A method comprising:
- traversing, via a host controller operatively coupled to at least one device, an asynchronous data transfer list to identify at least one data transfer to the at least one device to execute;
- entering a first sleep mode for the host controller in response to identifying no data transfers to execute and receiving an indication that a processor, operatively coupled to the host controller, is in a sleep state;
- exiting the first sleep mode for the host controller in response to receiving an indication that the processor is in a non-sleep state;
- entering a second sleep mode for the host controller in response to identifying no data transfers to execute and receiving an indication that the processor is in a non-sleep state;
- and
- exiting the second sleep mode in response to a lapse of a pre-determined time period.
An article of manufacture comprising a non-transitory machine-readable storage medium that provides instructions that, if executed by the machine, will cause the machine to perform operations comprising:
- traversing, via a host controller operatively coupled to at least one device, an asynchronous data transfer list to identify at least one data transfer to the at least one device to execute;
- entering a first sleep mode for the host controller in response to identifying no data transfers to execute and receiving an indication that a processor, operatively coupled to the host controller, is in a sleep state;
- exiting the first sleep mode for the host controller in response to receiving an indication that the processor is in a non-sleep state;
- entering a second sleep mode for the host controller in response to identifying no data transfers to execute and receiving an indication that the processor is in a non-sleep state;
- and
- exiting the second sleep mode in response to a lapse of a pre-determined time period.
An apparatus comprising:
- a processor to execute a plurality of executable logic of the apparatus, wherein the plurality of executable logic of the apparatus includes:
- logic to traverse an asynchronous data transfer list to identify at least one data transfer to at least one device to execute;
- logic to enter a first sleep mode in response to identifying no data transfers to execute and receiving an indication that a processor is in a sleep state;
- logic to exit the first sleep mode in response to receiving an indication that the processor is in non-sleep state;
- logic to enter a second sleep mode in response to identifying no data transfers to execute and receiving an indication that the processor is in a non-sleep state;
- and
- logic to exit the second sleep mode in response to a lapse of a pre-determined time period.
Dependencies are inferred from the claim text.