Power management for a system on a chip (SoC)
AssigneeIntel Corporation
InventorsWoojong Han, Madhu Athreya, Ken Shoemaker, Arvind Mandhani, Mahesh Wagh, Ticky Thakkar
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Abstract
In one embodiment, the present invention includes a method for sending a first link handshake signal between a first subsystem and a power management unit (PMU) of a system on a chip (SoC) to request entry into a power saving state for the first subsystem, sending a second link handshake signal between the first subsystem and the PMU to acknowledge the request, and placing the first subsystem into the power saving state without further signaling between the PMU and the first subsystem. Other embodiments are described and claimed.
Claims20
A method comprising:
- sending a first link handshake signal between a first subsystem of a first power domain and a power management unit (PMU) of a system on a chip (SoC) on a sideband channel coupled between the first subsystem and the PMU, the SoC further including a second subsystem heterogeneous to the first subsystem and controllable to be in a different power state than the first subsystem, the first link handshake signal to request entry into a power saving state for the first subsystem, the power saving state between consecutive device power states of an operating system (OS)-driven power management system;
- sending a second link handshake signal between the first subsystem and the PMU to acknowledge the request;
- and
- placing the first subsystem into the power saving state in response to the second link handshake signal without further signaling between the power management unit and the first subsystem.
A system comprising:
- a plurality of heterogeneous resources formed on a single semiconductor device;
- an interconnect of the single semiconductor device to communicate with the plurality of heterogeneous resources;
- and
- a power management unit (PMU) of the single semiconductor device to provide clock signals for each of the plurality of heterogeneous resources, wherein the PMU is to implement a common power management protocol across the plurality of heterogeneous resources independent of an operating system (OS) of the system, the common power management protocol to enable an intermediate power saving state between two consecutive device power state of an OS-driven power management system, wherein a first heterogeneous resource and a second heterogeneous resource are controllable to be maintained in different power states via the PMU.
A system-on-chip (SoC) comprising:
- a plurality of heterogeneous resources formed on a single semiconductor die;
- an interconnect of the single semiconductor die to communicate with the plurality of heterogeneous resources;
- and
- a power management unit (PMU) of the single semiconductor die to provide clock signals for at least some of the plurality of heterogeneous resources, wherein the PMU is to implement a power management protocol across the plurality of heterogeneous resources independent of an operating system (OS), the power management protocol to enable an intermediate power saving state between consecutive device power states of an OS-driven power management system.
Dependencies are inferred from the claim text.