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US 8,510,547 B2Granted
Power reduction for system on chip
AssigneeIntel Corporation
InventorsTeck Ee Guan, Kai Hoong Fong
Life of this patent
Estimating the term…
Abstract
Disclosed herein are SOC devices with peripheral units having power management logic.
Claims12
A system-on-a-chip integrated circuit, comprising:
- a processor core;
- a peripheral unit communicatively coupled to the processor core, the peripheral unit comprising power management logic to determine when the peripheral unit may go into a power reduction state and to request entry into the power reduction state;
- and
- a clock provided to the peripheral unit, the clock comprising clock control logic coupled between the processor core and the peripheral unit to provide the clock to the peripheral unit, wherein the clock control logic comprises a power mode status bit for the peripheral unit to indicate if the peripheral unit is in the power reduction state, wherein the power management logic comprises a separate power mode status bit that mirrors the power mode status bit in the clock control logic, and wherein the processor core causes the clock to be reduced in servicing the power reduction request through control of the power mode status bit.
1 more element
A method, comprising:
- within an SOC, receiving a power reduction request from a peripheral unit generated by power management logic within the peripheral unit;
- and
- sending a signal to cause power consumption in the peripheral unit to be reduced in response to the power reduction request, wherein power consumption is to be reduced by reducing a clock provided to the peripheral unit, the clock comprising clock control logic to provide the clock to the peripheral unit, wherein the clock control logic comprises a power mode status bit for the peripheral unit to indicate if the peripheral unit is in the power reduction state, wherein the power management logic comprises a separate power mode status bit that mirrors the power mode status bit in the clock control logic, and wherein the clock is reduced through control of the power mode status bit.
A wireless communications device, comprising:
- an SOC comprising a processor core, a peripheral unit communicatively coupled to the processor core, the peripheral unit having power management logic to determine when the peripheral unit may go into a power reduction state and to request entry into the power reduction state, and a clock provided to the peripheral, the clock comprising clock control logic coupled between the processor core and the peripheral unit to provide the clock to the peripheral unit, wherein the clock control logic comprises a power mode status bit for the peripheral unit to indicate if the peripheral unit is in the power reduction state, wherein the power management logic comprises a separate power mode status bit that mirrors the power mode status bit in the clock control logic, and wherein the processor core causes the clock to be reduced in servicing the power reduction request through control of the power mode status bit;
- an antenna coupled to the processor core through a wireless interface;
- and
- a serial communications interface coupled to the processor core through the peripheral unit.
1 more element
Dependencies are inferred from the claim text.