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AssigneeNational Tsing Hua University
InventorsChia Han Lu, Chung Ju Wu, Jenq Kuen Lee
Estimating the term…
A spilling method in register files for a processor is proposed. The processor with Parallel Architecture Core structure includes multiple clusters and a memory. Each cluster includes multiple function units (M-Unit and I-Unit), multiple local register files and a global register file. The local register files are used by the multiple function units, respectively. For a specified live range, the method includes calculating communication costs of the local register files and the global register file in each cluster, and communication cost of the memory for spilling the live range when spilling occurs; calculating use ratios of the local register files and the global register file in each cluster, and use ratio of the memory for the live range; and selecting one of the local register files and the global register file in each cluster and the memory for spilling the live range based on the communication costs and use ratios.
A spilling method in register files for a processor, the processor comprising a first cluster, a second cluster and a memory, each of the first and second clusters comprising a first function unit, a second function unit, a first local register file, a second local register file and a global register file, the first and second local register files being used by the first and second function units, respectively;
Dependencies are inferred from the claim text.
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Register arrangements: organisation of register space, e.g. banked or distributed register file
Controlled by multiple instructions, e.g. MIMD, decoupled access or execute: organised in groups of units sharing resources, e.g. clusters
Computing and data processing
About 5 years 2 months of term left · ends 10 Jan 2032 (estimated)
(A) Field of the Invention
The present invention is related to a spilling method in register files for a microprocessor, and more particularly, to a spilling method in register files applied to a Parallel Architecture Core (PAC) processor.
(B) Description of the Related Art
FIG. 1 illustrates the processor architecture in accordance with the present invention;
FIG. 2 illustrates the setting of the communication costs of an instruction of the register files in accordance with an embodiment of the present invention;
FIG. 3 and FIG. 4 illustrate the calculation of the use ratio of the register file in accordance with an embodiment of the present invention; and
The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.
This embodiment is primarily applied to VLIW DSP with PAC architecture.
FIG. 1 shows a PAC processor 10 including a first cluster 1 and a second cluster 2. The cluster 1 and the cluster 2 each include a first function unit 20, a second function unit 30, a first local register file A1 or A2 connected to the first function unit 20, a second local register file AC1 or AC2 connected to the second function unit 30, and a global register file D1 or D2. The PAC processor 10 further includes an independent third function unit 40 outside the first cluster 1 and the second cluster 2, and a third local register file R connected to the third function unit 40. The first function units 20 of the first cluster 1 and the second cluster 2 and the third function unit 40 are connected to a memory 50.