Vector completion mask handling
AssigneeIntel Corporation
InventorsStephan Jourdan, Michael Fetterman, Michael Cornaby, Per Hammarlund, Ronak Signhal, Glenn Hinton
Life of this patent
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Abstract
Techniques for vector completion mask (VCM) handling are provided. A data structure includes a mask field for each operand of a particular operation. A processor attempts to execute the operation with multiple operands, which are identified in the data structure by the mask fields. If operands are successfully retrieved for execution with the operation, then the corresponding mask field within the data structure is cleared. The processor can reset if any field remains set within the data structure and can re-process the operation with operands that were not previously handled with the operation.
Claims17
A processor comprising:
- at least one execution unit;
- and
- a vector completion mask (VCM) logic to store information into at least one VCM register, the at least one VCM register to hold a plurality of bits each associated with at least one operand, wherein the VCM logic is to change a first bit stored in the at least one VCM register to a first state if a first operation using a first operand associated with the first bit is successfully processed in the at least one execution unit, wherein the first bit is of a second state to indicate that the first operation using the first operand has not been successfully processed in the at least one execution unit, and the processor is to reset, re-evaluate the at least one VCM register, and re-process the first operation if after a prior execution of the first operation a bit of the second state remains within the at least one VCM register.
A method comprising:
- associating multiple operands with a single operation within a processor;
- processing the operation in an execution unit of the processor with each of the operands that are available to process;
- clearing a flag within a data structure for each operand that is successfully processed in the execution unit with the operation, wherein a bit of a set state in the data structure indicates that the operation has not been successfully processed in the at least one execution unit for a corresponding operand and the bit of a reset state indicates that the operation has been successfully processed in the at least one execution unit for the corresponding operand;
- flushing contents of the processor;
- evaluating the data structure to reprocess the operation for select ones of the operands that are identified within the data structure as having set flags;
- and
- clearing a set flag within the data structure for each operand that is successfully processed with the operation.
A system comprising:
- a processor including a logic to access and manage a vector completion mask (VCM) register, wherein the logic is to update a bit of the VCM register if an operand associated with the bit is successfully retrieved and processed with an operation in an execution unit of the processor, wherein a bit of a first state in the VCM register is to indicate that a corresponding operand should be operated upon in the execution unit and the bit of a second state is to indicate that the corresponding operand should not be operated upon in the execution unit, wherein the processor is to reset, re-evaluate the VCM register, and re-process the operation if after a prior execution of the operation a set bit of the first state remains within the VCM register;
- and
- memory coupled to the processor.
Dependencies are inferred from the claim text.