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US 8,510,493 B2Granted
Circuit to efficiently handle data movement within a cache controller or on-chip memory peripheral
AssigneeLSI Corporation
InventorsJudy M Gehman, Jerome M Meyer
Life of this patent
Estimating the term…
Abstract
The present invention is directed to a circuit for managing data movement between an interface supporting the PLB6 bus protocol, an interface supporting the AMBA AXI bus protocol, and internal data arrays of a cache controller and/or on-chip memory peripheral. The circuit implements register file buffers for gathering data to bridge differences between the bus protocols and bus widths in a manner which addresses latency and performance concerns of the overall system.
Claims16
A controller, comprising:
- a command and control processing subsystem;
- a bus interface, the bus interface configured for being communicatively coupled with the command and control processing subsystem;
- an array interface, the array interface configured for being communicatively coupled with the command and control processing subsystem;
- and
- a memory controller interface, the memory controller interface configured for being communicatively coupled with the command and control processing subsystem, wherein the command and control processing subsystem includes:
- a Write Address Control (WAC) partition, a Read Address Control (RAC) partition, a Write Data Flow (WDF) partition, and a Read Data Flow (RDF) partition, the RAC partition is configured for generating read requests for the memory controller interface and for providing said generated read requests to the memory controller interface, the WAC partition is configured for generating write requests for the memory controller interface and for providing said generated write requests to the memory controller interface, the WAC partition is configured for receiving:
- write requests from the bus interface, cache maintenance operations from a Device Control Register (DCR) partition, and cache push requests from the array interface.
4 more elements
A controller, comprising:
- a command and control processing subsystem, the command and control processing subsystem including:
- a Write Address Control (WAC) partition, a Read Address Control (RAC) partition, a Write Data Flow (WDF) partition, and a Read Data Flow (RDF) partition, the WDF partition including a first register file memory and a second register file memory, the RDF partition including a first register file memory and a second register file memory;
- a Processor Local Bus (PLB) interface, the PLB interface configured for being communicatively coupled with the command and control processing subsystem;
- an array interface, the array interface configured for being communicatively coupled with the command and control processing subsystem;
- and
- an Advanced eXtensible Interface (AXI) interface, the AXI interface configured for being communicatively coupled with the command and control processing subsystem,
- wherein eviction data from the array interface writes into the first register file memory of the WDF partition via a first data path, while write data received via the PLB interface is written into the second register file memory of the WDF partition via a second data path, said second data path being separate from said first data path, said writing of the eviction data into first register file memory and said writing of the write data received via the PLB interface into the second register file memory occurring concurrently.
4 more elements
A controller, comprising:
- a command and control processing subsystem, the command and control processing subsystem including:
- a Write Address Control (WAC) partition, a Read Address Control (RAC) partition, a Write Data Flow (WDF) partition, and a Read Data Flow (RDF) partition, the WDF partition including a first register file memory and a second register file memory, the RDF partition including a first register file memory and a second register file memory;
- a Processor Local Bus (PLB) interface, the PLB interface configured for being communicatively coupled with the command and control processing subsystem, the PLB interface configured for receiving write data from a PLB bus and providing the write data to the command and control processing subsystem;
- an array interface, the array interface configured for being communicatively coupled with the command and control processing subsystem;
- and
- an Advanced eXtensible Interface (AXI) interface, the AXI interface configured for being communicatively coupled with the command and control processing subsystem, the AXI interface configured for receiving read data from an AXI bus and providing the read data to the command and control processing subsystem,
- wherein the second register file memory of the RDF partition is configured for receiving the read data provided by the AXI interface, the second register file memory of the RDF partition being further configured for transferring said received read data to at least one of:
- the PLB interface and the array interface, the second register file memory of the WDF partition is configured for receiving the write data provided by the PLB interface, the second register file memory of the WDF partition being further configured for transferring said received write data to at least one of:
- the AXI interface and the array interface.
6 more elements
Dependencies are inferred from the claim text.