US 8,510,485 B2Granted

Low power digital interface

AssigneeApple Inc.

InventorsThomas James Wilson, Yutaka Hori

Life of this patent

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Abstract

This relates to interface circuits for synchronous protocols which do not rely on a dedicated high frequency clock signal. Instead, the interface circuit may rely on a clock signal received over the interface from another device in order to transfer data between the interface and an internal buffer. Furthermore, the interface circuits can rely on a clock signal provided by a bus for a device the interface circuit is located in to transfer data between the internal buffer and the bus. The internal buffer can be, but is not limited to a FIFO. Alternatively, it can be a stack or another data structure. The internal buffer can be configured so that each of its multiple of cells is a shift register. Thus, a preparatory step of moving a byte of data from the buffer to a separate shift register can be avoided.

Claims40

Dependent claims

An master/slave serial peripheral interface (SPI) circuit comprising:

a master SPI interface including:
a master serial data output line;
a master serial data input line;
a master output interface clock line for transmitting interface clock signals;
and
a slave SPI interface including:
a slave serial data input line connected to the master serial data output line;
a slave serial data output line connected to the master serial data input line;
a slave input interface clock line connected to the master output interface clock line for receiving the interface clock signals from the master SPI interface;
a buffer having a plurality of cells, each cell having a clock input for receiving the interface clock signals from the slave input interface clock line and operative to output data bits in response to the interface clock signals;
a multiplexer having inputs connected to outputs of each of the plurality of cells of the buffer and an output provided as the slave serial data output line;
a demultiplexer having an input connected to receive the interface clock signals and outputs connected to the clock inputs of the plurality of cells;
a read pointer processing circuit for generating a read pointer;
the multiplexer connected to receive the read pointer for connecting as an input thereto only a selected output of a cell designated by the read pointer;
the demultiplexer connected to receive the read pointer for connecting the interface clock signals from the serial input interface clock line connected to the master output interface clock line to only a selected output thereof for feeding the interface clock signals to the clock input of the cell designated by the read pointer;
the clock input of the cell designated by the read pointer receiving the interface clock signals and outputting the data bits stored therein in synchronism with the interface clock signals,
wherein
the multiplexer outputs the data bits stored it the cell designated by the read pointer over the slave serial data output line in synchronism with the interface clock signals without reference to a dedicated high frequency clock signal.

15 more elements

An master/slave serial peripheral interface (SPI) circuit comprising:

a master SPI interface including:
a master serial data output line;
a master serial data input line;
an master output interface clock line for transmitting interface clock signals;
a slave SPI interface including:
a slave serial data input line connected to the master serial data output line;
a slave serial data output line connected to the master serial data input line;
a slave input interface clock line connected to the master output interface clock line for receiving the interface clock signals from the master SPI interface;
a buffer circuit including a plurality of shift register cells, each cell having a clock input for receiving the interface clock signals from the slave input interface clock line and operative to store data bits therein and to output the data bits in response to the interface clock signals;
a pointer circuit for generating a pointer for designating ones of the plurality of cells of the buffer;
wherein
the buffer circuit is operative, in response to the pointer and the interface clock signals for transmitting data bits from the designated ones of the plurality of cells to the slave serial data output line in synchronism with the interface clock signals received from the slave input interface clock line.

9 more elements

A slave interface in a master/slave peripheral interface SPI circuit having a master SPI, the slave interface comprising:

a slave SPI interface including:
a slave serial data input line;
a slave serial data output line;
a slave input interface clock line connectable to receive interface clock signals from the master SPI interface;
a buffer having a plurality of cells, each cell having a clock input for receiving the interface clock signals from the slave input interface clock line and operative to output data bits in response to the interface clock signals;
a multiplexer having inputs connectable to outputs of each of the plurality of cells of the buffer and an output provided as the slave serial data output line;
a demultiplexer having an input connectable to receive the interface clock signals and outputs connected to the clock inputs of the plurality of cells;
a read pointer processing circuit for generating a read pointer;
the multiplexer connected to receive the read pointer for connecting as an input thereto only a selected output of a cell designated by the read pointer;
the demultiplexer connected to receive the read pointer for connecting the interface clock signals from the serial input interface clock line connected to a master output interface clock line to only a selected output thereof for feeding the interface clock signals to the clock input of the cell designated by the read pointer;
the clock input of the cell designated by the read pointer receiving the interface clock signals and outputting the data bits stored therein in synchronism with the interface clock signals,
wherein
the multiplexer outputs the data bits stored in the cell designated by the read pointer over the slave serial data output line in synchronism with the interface clock signals without reference to a dedicated high frequency clock signal.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/947,723Filed 29 Nov 2007 · us provisional application
Priority: 31 Aug 2007
Published: US 2009/0063736 A15 Mar 2009
Granted: 13 Aug 2013
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

G06F 13/4291
On a serial bus, e.g. I2C bus, SPI bus: using a clocked protocol
G06F 5/10
For changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor: having…
Y02D 10/00
Energy efficient computing
G06F
Computing and data processing