Data processing system having peripheral-paced DMA transfer and method therefor

In a data processing system having a processor, a direct memory access (DMA) controller, a peripheral that is distinct from the DMA controller, and a memory, wherein the peripheral provides a data request signal to the DMA controller and the DMA controller provides a data request enable signal to the peripheral, a method comprising:

• asserting the data request enable signal, by the DMA controller, which initiates a data transfer between the peripheral and the memory, wherein the data transfer comprises N subsets of data to be transferred between the peripheral and the memory, N having a value of two or more;
• asserting, by the peripheral, an event status indicator each time an event is completed by the peripheral;
• in response to each assertion of the event status indicator and while the request enable signal is asserted, the peripheral asserting the data request signal provided to the DMA controller;
• in response to an assertion of the event status indicator and a deassertion of the data request enable signal, the peripheral asserting an interrupt request that is provided to the processor without involvement of the DMA controller to indicate completion of the data transfer, whereas the interrupt request is not asserted by the peripheral prior to completion of the transfer;
• in response to each assertion of the data request signal, the DMA controller initiating transfer of a next subset of data of the N subsets of data between the memory and the peripheral;
• and
• in response to the DMA controller determining that the next subset of data is a last subset of data to be transferred between the memory and the peripheral, the DMA controller deasserting the data request enable signal.

A data processing system, comprising:

• a processor coupled to a system interconnect;
• a memory coupled to the system interconnect;
• a peripheral coupled to the system interconnect, the peripheral comprising a status indicator which is asserted each time a peripheral function is completed by the peripheral;
• and
• a DMA controller coupled to the system interconnect and distinct from the peripheral, wherein the DMA controller asserts a data request enable signal which initiates a data transfer between the peripheral and the memory, wherein the data transfer comprises N subsets of data to be transferred between the peripheral and the memory, N having a value of two or more, and wherein the DMA controller deasserts the data request enable signal in response to determining that a next subset of data to be transferred is a last subset of data to be transferred;
• wherein, in response to each assertion of the status indicator, the peripheral, based on the data request enable signal received from the DMA controller, performs one of:
• asserting a data request signal which is provided to the DMA controller when the data request enable signal is asserted, wherein, in response to each assertion of the data request signal by the peripheral, the DMA controller initiates transfer of a next subset of data of the N subsets of data between the memory and the peripheral, or
• when the data request enable signal is deasserted, asserting an interrupt request that is provided to the processor without involvement of the DMA controller to indicate completion of the data transfer, whereas the interrupt request is not asserted by the peripheral prior to completion of the transfer.