SIMD sign operation
AssigneeIntel Corporation
InventorsWilliam W. Macy, Jr., Huy V. Nguyen
Life of this patent
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Abstract
Method, apparatus, and program means for nonlinear filtering and deblocking applications utilizing SIMD sign and absolute value operations. The method of one embodiment comprises receiving first data for a first block and second data for a second block. The first data and said second data are comprised of a plurality of rows and columns of pixel data. A block boundary between the first block and the second block is characterized. A correction factor for a deblocking algorithm is calculated with a first instruction for a sign operation that multiplies and with a second instruction for an absolute value operation. Data for pixels located along said block boundary between the first and second block are corrected.
Claims4
A system-on-chip (SoC) comprising:
- a memory of the SoC;
- a memory controller of the SoC, the memory controller coupled with the memory;
- a digital signal processor (DSP) of the SoC, the DSP coupled with the memory and the memory controller, the DSP comprising:
- a plurality of registers, wherein the plurality of registers are operable to store 64-bit packed data operands and 128-bit packed data operands;
- a decoder to decode a Single Instruction Multiple Data (SIMD) instruction, the SIMD instruction to have a 32-bit instruction format, the SIMD instruction to have a first field to indicate a first 64-bit source packed data operand that is to be stored in the plurality of registers, and the SIMD instruction to have a second field to indicate a second 64-bit source packed data operand that is to be stored in the plurality of registers, the first 64-bit source packed data operand to include a first four 16-bit data elements, and the second 64-bit source packed data operand to include a second four 16-bit data elements, each of the 16-bit data elements of the first 64-bit source packed data operand corresponding to one of the 16-bit data elements of the second 64-bit source packed data operand;
- and
- an execution unit coupled with the decoder and the plurality of registers, the execution unit in response to the SIMD instruction, to store a 64-bit destination packed data operand that is to be indicated by a third field of the SIMD instruction in the plurality of registers, the 64-bit destination packed data operand to include four 16-bit result data elements, wherein,
- for each positive 16-bit data element of the first 64-bit source packed data operand, a corresponding 16-bit data element of the second 64-bit source packed data operand is to be stored in a corresponding 16-bit result data element, and
- for each negative 16-bit data element of the first 64-bit source packed data operand, a negative of a corresponding 16-bit data element of the second 64-bit source packed data operand is to be stored in a corresponding 16-bit result data element, and
- wherein the DSP is a very long instruction word (VLIW) processor.
Dependencies are inferred from the claim text.