Logic structures and methods supporting pipelined multi-operand adders
AssigneeAltera Corporation
InventorMartin Langhammer
Life of this patent
Estimating the term…
Abstract
Circuitry for adding together three long numbers may include the formation of redundant form sum bit signals and redundant form carry bit signals. These signals may be finally combined in a ripple carry adder chain that produces sum bit output signals and ripple carry bit signals. Both a ripple carry bit signal and a redundant form carry bit signal must be passed from the circuitry performing each place of the addition to the circuitry performing the next-more-significant place of the addition. Various techniques are disclosed for facilitating subdividing long chains of such circuitry, as well as possibly including (between such subdivisions) “pipeline” registers for both ripple and redundant form carry bit signals.
Claims15
A method of operating an integrated circuit that includes a plurality of subregions of logic module circuitry, each of the subregions being capable of producing (1) a redundant form sum bit signal from addition of a respective group of three input bit signals, and (2) a redundant form carry bit signal from said addition, and each of the subregions including ripple carry adder circuitry for producing a ripple carry bit signal, only a subset of said subregions being used for addition of input bit signals to produce redundant form sum bit signals of input bit signals up to a predetermined threshold arithmetic significance, the method comprising:
- setting all of the subregions that can produce ripple carry bit signals having arithmetic significance greater than the threshold to propagate the ripple carry bit signal from the subregion having the threshold arithmetic significance;
- and
- re-applying to the subregion that can produce the ripple carry bit signal having greatest arithmetic significance the input bit signals having the threshold arithmetic significance.
A method of operating an integrated circuit that includes a plurality of subregions of logic module circuitry, each of the subregions being capable of producing (1) a redundant form sum bit signal from addition of a respective group of three variable input bit signals, and (2) a redundant form carry bit signal from said addition, and each of the subregions including ripple carry adder circuitry for producing a ripple carry bit signal, only a subset of said subregions being used for addition of variable input bit signals to produce redundant form sum bit signals up to a predetermined threshold arithmetic significance, the method comprising:
- setting a first subregion, that is not part of the subset but that can receive a ripple carry bit signal from the subregion having the threshold arithmetic significance, to output the received ripple carry bit signal as a first region output signal of a region of circuitry that includes said subregions;
- re-applying to a second subregion that is not part of the subset the variable input bit signals that are applied to the subregion having the threshold arithmetic significance;
- and
- setting the second subregion to output as a second region output signal of said region a signal indicative of the majority of the variable input bit signals that are re-applied to the second subregion.
A method of operating an integrated circuit that includes a plurality of subregions of logic module circuitry, each of the subregions being capable of producing (1) a redundant form sum bit signal from addition of a respective group of three variable input bit signals, and (2) a redundant form carry bit signal from said addition, and each of the subregions including ripple carry adder circuitry for producing a ripple carry bit signal, only a subset of said subregions being used for addition of variable input bit signals up to a predetermined threshold arithmetic significance, the method comprising:
- applying, to a first subregion that receives the redundant form and ripple carry bit signals from the subregion having the threshold arithmetic significance, predetermined input bit signals that cause the first subregion to produce a first region output signal of a region of circuitry that includes the subregions;
- applying, to a second subregion that receives the redundant form and ripple carry bit signals from the first subregion, predetermined input bit signals that cause the second subregion to produce a second region output signal of said region, the first and second region output signals including signal information from which the ripple carry bit signal having the threshold arithmetic significance can be determined;
- re-applying to a third subregion that is not part of the subset the variable input bit signals having the threshold arithmetic significance;
- and
- setting the third subregion to output as a third region output signal of said region a signal indicative of a majority of the variable input bit signals that are re-applied to the third subregion.
Dependencies are inferred from the claim text.