Bitstream buffer manipulation with a SIMD merge instruction
AssigneeIntel Corporation
InventorsYen-Kuang Chen, William W. Macy, Jr., Matthew Holliman, Eric L. Debes, Minerva M. Yeung
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Abstract
Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block.
Claims25
A method in a processor comprising:
- determining that unprocessed data bits for a partial variable length symbol exist in a first data block;
- and
- performing a shift merge operation in response to an instruction decoded by the processor using circuitry of the processor to merge said unprocessed data bits from said first data block with a second data block to form a merged data block,
- wherein said shift merge operation operates at a byte granularity, and wherein the instruction indicates a number of bytes to indicate the unprocessed data bits from the first data block.
An apparatus comprising:
- a decode unit to decode a first instruction of a variable length decoding algorithm, the first instruction for a shift merge operation;
- and
- an execution unit coupled with the decode unit, the execution unit including circuitry responsive to decode of the first instruction to:
- perform a shift merge operation to merge unprocessed data bits for a partial variable length symbol from a first data block with a second data block to form a merged data block,
- wherein said shift merge operation uses a byte granularity, and wherein the first instruction specifies a number of bytes to indicate the unprocessed data bits from the first data block.
An apparatus comprising:
- a plurality of registers to store packed data operands;
- a decode unit to decode a single instruction multiple data (SIMD) instruction, the SIMD instruction to indicate a first packed data operand having a first set of M bytes and a second packed data operand having a second set of M bytes, the SIMD instruction to have an immediate to specify a number (n) of bytes;
- an execution unit coupled with the decode unit and the plurality of registers, the execution unit, in response to the decode unit decoding the SIMD instruction, to store a packed data result in a destination indicated by the SIMD instruction, wherein the packed data result is to include, the number (n) least significant bytes of the second packed data operand in the number (n) most significant bytes of the packed data result,
- concatenated with M minus the number (n) most significant bytes of the first operand in M minus the number (n) least significant bytes of the result;
- a flash memory interface;
- a synchronous dynamic random access memory (SDRAM) interface;
- a universal serial bus (USB) interface;
- and
- a wireless universal asynchronous receiver/transmitter (UART) interface.
Dependencies are inferred from the claim text.