US 8,509,516 B2 · Circuit pattern examining apparatus and circuit pattern examining method

Abstract

Provided is an examination technique to detect defects with high sensitivity at an outer-most repetitive portion of a memory mat of a semiconductor device and even in a peripheral circuit having no repetitiveness. A circuit pattern inspection apparatus comprises an image detection unit for acquiring an image of a circuit pattern composed of multiple die having a repetitive pattern, a defect judgment unit which composes, in respect of an acquired detected image, reference images by switching addition objectives depending on regions of repetitive pattern and the other regions and compares a composed reference image with the detected image to detect a defect, and a display unit for displaying the image of the detected defect.

Claims13

Dependent claims

A circuit pattern inspection apparatus, comprising:

an image detection unit configured to acquire an image of a circuit pattern composed of multiple die having a repetitive pattern;
and
a defect judgment unit configured to:
compose, in respect of a divided detected image of the acquired image, reference images by switching addition objects depending on regions of the repetitive pattern and other regions, and
compare at least one of the composed reference images with the detected image to detect a defect,
wherein the defect judgment unit is configured to, when a region of the repetitive pattern is included in divided detected images of the acquired image, compose the reference images by adding a portion of the repetitive pattern thereto in a repetition direction that is determined by a position of a region corresponding to the divided detected images.

3 more elements

Dependencies are inferred from the claim text.

Circuit pattern examining apparatus and circuit pattern examining method

Life of this patent

Circuit pattern examining apparatus and circuit pattern examining method

Life of this patent

Abstract

Claims13