Multi-band clock generator with adaptive frequency calibration and enhanced frequency locking
AssigneeIntegrated Device Technology, Inc.
InventorsYu Zhang, Changming Wei
Life of this patent
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Abstract
A multi-band clock generator includes a phase-locked loop (PLL) integrated circuit responding to first and second clock signals, and includes a multi-band voltage controlled oscillator (VCO) responding to a multi-bit control word that sets a frequency characteristic curve of the VCO. The multi-band clock generator also includes an adaptive frequency calibration (AFC) circuit responding to the first and second clock signals, and the AFC circuit is configured to look-up a first multi-bit control word during an operation to lock an output clock signal generated by the VCO to a first frequency characteristic curve associated with the first multi-bit control word.
Claims21
A multi-band clock generator, comprising:
- a phase-locked loop (PLL) integrated circuit responsive to first and second clock signals, said PLL integrated circuit having a multi-band voltage-controlled oscillator (VCO) therein responsive to a multi-bit control word that selects a frequency sub-band of the VCO;
- and
- an adaptive frequency calibration (AFC) circuit responsive to the first and second clock signals, said AFC circuit configured to look-up an estimate of a target multi-bit control word, which is derived from a previously-determined control word having a value associated with a frequency lock of the multi-band clock generator and stored in a programmable device, during an operation to lock an output clock signal generated by the VCO to a frequency sub-band associated with the target multi-bit control word.
A multi-band clock generator, comprising:
- a phase-locked loop (PLL) integrated circuit responsive to first and second clock signals, said PLL integrated circuit having a multi-band voltage-controlled oscillator (VCO) therein responsive to a multi-bit control word that selects a frequency sub-band of the VCO;
- and
- an adaptive frequency calibration (AFC) circuit responsive to the first and second clock signals, said AFC circuit configured to select a first multi-bit control word using a multi-directional jumping algorithm that jumps a plurality of multi-bit control words during an operation to lock an output clock signal generated by the VCO to a frequency sub-band associated with a target multi-bit control word.
A multi-band clock generator, comprising:
- a phase-locked loop (PLL) integrated circuit responsive to first and second clock signals, said PLL integrated circuit having a multi-band voltage-controlled oscillator (VCO) therein responsive to a multi-bit control word that sets a frequency characteristic curve of the VCO;
- and
- an adaptive frequency calibration (AFC) circuit responsive to the first and second clock signals, said AFC circuit configured to look-up an estimate of a target multi-bit control word, which is derived from a previously-determined lock condition associated with the multi-hand clock generator and stored in a programmable device, during an operation to lock an output clock signal generated by the VCO to a first frequency characteristic curve associated with the target multi-bit control word.
Dependencies are inferred from the claim text.