Continuous-rate clock recovery circuit
AssigneeAnalog Devices, Inc.
InventorJohn G. Kenney
Life of this patent
Estimating the term…
Abstract
A continuous-rate clock and data recovery circuit includes a delay locked loop with a first integrator and a phase locked loop with a separate integrator. The delay locked loop and the phase locked loop are in a dual loop architecture. The first integrator is a digital accumulator that wraps upon exceeding a maximum or minimum value. The second integrator is a digital accumulator that saturates at its maximum or minimum value.
Claims24
A continuous-rate clock and data recovery circuit, the circuit comprising:
- a delay locked loop with a phase shifter, wherein the delay locked loop comprises a first digital integrator;
- a phase locked loop with a digitally tunable oscillator, wherein the phase locked loop comprises a second digital integrator;
- and
- a phase detector,
- wherein the delay locked loop with the phase shifter and the phase locked loop with the digitally tunable oscillator are in a dual loop architecture, and
- wherein the phase detector is configured to control the first and second digital integrators.
A continuous-rate clock and data recovery circuit, the circuit comprising:
- a delay locked loop with an infinite phase shifter;
- and
- a phase locked loop with a digitally tunable oscillator,
- wherein the delay locked loop with the infinite phase shifter and the phase locked loop with the digitally tunable oscillator are in a dual loop architecture,
- the delay locked loop with the infinite phase shifter comprising a digital accumulator and a bits-to-phase interpolator.
A continuous-rate clock and data recovery circuit, the circuit comprising:
- a delay locked loop with an infinite phase shifter;
- and
- a phase locked loop with a digitally tunable oscillator, the phase locked loop comprising a first digital accumulator and a second digital accumulator,
- wherein the delay locked loop with the infinite phase shifter and the phase locked loop with the digitally tunable oscillator are in a dual loop architecture,
- wherein the first digital accumulator saturates at a minimum and at a maximum value.
A continuous-rate clock and data recovery circuit, the circuit comprising:
- a delay locked loop with an infinite phase shifter;
- and
- a phase locked loop with a digitally tunable oscillator, the phase locked loop comprising a first digital accumulator and a second digital accumulator,
- wherein the delay locked loop with the infinite phase shifter and the phase locked loop with the digitally tunable oscillator are in a dual loop architecture,
- wherein the second digital accumulator compensates for center frequency drift of the digitally tuned oscillator.
A continuous-rate clock and data recovery circuit, the circuit comprising:
- a delay locked loop with an infinite phase shifter;
- and
- a phase locked loop with a digitally tunable oscillator, the phase locked loop comprising a first digital accumulator and a second digital accumulator,
- wherein the delay locked loop with the infinite phase shifter and the phase locked loop with the digitally tunable oscillator are in a dual loop architecture,
- wherein the second accumulator adjusts the digitally tuned oscillator so that the first digital accumulator locks at a mid-value.
A continuous-rate clock and data recovery circuit, the circuit comprising:
- a delay locked loop with an infinite phase shifter;
- and
- a phase locked loop with a digitally tunable oscillator, the phase locked loop comprising a first digital accumulator and a second digital accumulator,
- wherein the delay locked loop with the infinite phase shifter and the phase locked loop with the digitally tunable oscillator are in a dual loop architecture,
- wherein a jitter transfer bandwidth of the first digital accumulator is programmable.
A continuous-rate clock and data recovery circuit, the circuit comprising:
- a delay locked loop with an infinite phase shifter;
- a phase locked loop with a digitally tunable oscillator;
- and
- a binary phase detector,
- wherein the delay locked loop with the infinite phase shifter and the phase locked loop with the digitally tunable oscillator are in a dual loop architecture,
- the delay locked loop comprising a first digital accumulator, the phase lock loop comprising a second digital accumulator, wherein the first digital accumulator is clocked at a rate N times a rate at which the second digital accumulator is clocked and N times a rate at which an output of the binary phase detector changes.
A method for generating a continuous-rate clock, the method comprising:
- receiving a clock signal at a delay lock loop and phase lock loop;
- in the delay lock loop, adjusting the clock signal by increasing a phase offset of the clock signal based on a value of a first digital accumulator and a look-ahead value;
- in the phase lock loop, adjusting control logic of a source of the clock signal based on a value of a second digital accumulator;
- and
- adjusting control logic of the source of the clock signal such that the value of the second digital accumulator locks on a mid-value.
A method for generating a continuous-rate clock, the method comprising:
- receiving a clock signal at a delay lock loop and phase lock loop;
- in the delay lock loop, adjusting the clock signal by increasing a phase offset of the clock signal based on a value of a first digital accumulator and a look-ahead value;
- in the phase lock loop, adjusting control logic of a source of the clock signal based on a value of a second digital accumulator;
- and
- cleaning jitter from a recovered clock signal by absorbing timing difference between the clock signal and an adjusted clock signal.
Dependencies are inferred from the claim text.